A 252Kgates/4.9Kbytes SRAM/71mW Multi-Standard Video Decoder for High Definition Video Applications

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A 252Kgates/4.9Kbytes SRAM/71mW Multi-Standard
Video Decoder for High Definition Video
Applications

• Motivation
• A variety of video coding standards
• Increasing demands on versatile multimedia
  devices
• Target
• A multi-standard video decoder for real-time HD
  video (HD1080) applications
• Design Goals
• Low hardware cost
• Low memory bandwidth

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Proposed Techniques

• Reducing design complexity
• Hybrid block level pipeline control
• Shared adder-based filter structure
• Reducing memory bandwidth
• Hybrid block access
• Dual block access
• Reducing memory access latency
• Optimized 2-D block access
• Low latency memory control scheme

Reducing 4060 complexity
Reducing 3756 memory bandwidth
Reducing 3841 memory bandwidth
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Chip Summary

• Chip implementation
• Chip prototyping

• Acknowledgements
• National Science Council, Taiwan
• Minister of Economic Affairs, Taiwan
• Chip Implementation Center, Taiwan