Impact of Guardband Reduction on Design Process Outcomes

1
Impact of Guardband Reduction on Design Process
Outcomes

• Kwangok Jeong (kjeong_at_vlsicad.ucsd.edu)
• Andrew B. Kahng (abk_at_cs.ucsd.edu)
• Kambiz Samadi (kambiz_at_vlsicad.ucsd.edu)
• University of California, San Diego

2
Outline

• Motivation
• Background
• Model Guardband Reduction
• Design Flow Test Cases
• Experimental Results
• Discussion Impact on Yield
• Conclusion

3
Is High Yield ALWAYS Better?

• High yield is a general target of IC
  manufacturing
• But, more design effort and larger guardband are
  required to make a chip immune to process /
  environment variations

4
How Much Benefit Comes From DFM?

• Many techniques claim to reduce guardband by X.
• Gupta et. al (DAC 04) 40 guardband reduction
  by adopting iso-dense variational timing analysis
• Sylvester et. al (VLSITSA99) 60 of BEOL
  guardband reduction
• What is the value or cost of guardband?
• Designer Minimize guardband
• Foundry Maximize guardband
• The impact of guardband on design process
  outcomes has never been quantified before.

How to decide it?
5
Outline

• Motivations
• Background
• Model Guardband Reduction
• Design Flow Test Cases
• Experimental Results
• Discussion Impact on Yield
• Conclusion

6
Why do we need guardband?

• Cloud of uncertainties
• Guardband should cover the uncertainties
• High coverage of variations lead to high yield
• Variability tolerance has been increased (cf.
  ITRS 2005)

7
Guardband vs. Design Outcomes

• Delay of the setup critical path must be fast at
  the worst corner
• Increasing drive strength of cells

• Delay of the hold critical path must be slow at
  the best corner
• Inserting delay cells

8
Outline

• Motivations
• Background
• Model Guardband Reduction
• Design Flow Test Cases
• Experimental Results
• Discussion Impact on Yield
• Conclusion

9
Traditional Guardband

• Example of the guardband
• We model the reduction of both FEOL and BEOL
  guardband

Process Process Process Process Voltage Temp.
FEOL FEOL BEOL BEOL Voltage Temp.
NMOS PMOS Cap. Res. Voltage Temp.
WORST Slow Slow Max. Min. Low (e.g. 0.9V) High (e.g. 125?C)
BEST Fast Fast Min. Max High (e.g. 1.1V) Low (e.g. -40 ?C)
10
FEOL Guardband Liberty Model Scaling

• Cell delay and Transition time
• M x M table
• Function (Input slew, Output load)
• Input capacitance
• 1 x 1 table

• Guard Band Reduction
• Reduce guardband evenly between best and worst
  corners

11
FEOL Guardband Reduction

• Goal Entry-by-Entry BC-WC Guardband Reduction

Original Worst
Original Best
Input best/worst-case libraries. Output index-matched best-case library.
for all the cells in the best-case library Find the corresponding cell in the worst case library. interpolate/extrapolate the new best-case timing table entries using the best/worst-case values. copy the slew rate index of the worst-case table on to that of the best-case table.
1 2 3 4
1 1 1 1 1
2 2 2 2 2
3 3 3 3 3
4 4 4 4 4
1 2 3 4
2 4 4 4 4
4 6 6 6 6
6 8 8 8 8
5 10 10 10 10
Inter/extra-polation w/ worst indices
Index Matched Best
1 2 3 4
2 2 2 2 2
3 3 3 3 3
4 4 4 4 4
5 5 5 5 5
Move toward best value
Input index-matched best/worst-case libraries and x guardband reduction Output guardband reduced best/worst-case libraries.
for all the cells in the best/worst-case libraries for each entry in a best-case table (valuebest ) (valuebestvaluebest x/200? (valueworst-valuebest) for each entry in a worst-case table (valueworst ) (valueworstvaluebest- x/200? (valueworst-valuebest )
Move toward worst value
New Best
New Worst
1 2 3 4
2 2.1 2.1 2.1 2.1
3 3.15 3.15 3.15 3.15
4 4.2 4.2 4.2 4.2
5 5.25 5.25 5.25 5.25
1 2 3 4
2 3.9 3.9 3.9 3.9
3 5.85 5.85 5.85 5.85
4 7.8 7.8 7.8 7.8
5 9.75 9.75 9.75 9.75
12
BEOL Guardband SOCEncounter

• Resistance worst case is 1.16X greater than best
• Major parameter Temperature
• Capacitance worst case is 1.11X greater than
  best
• Major parameter Process

Resistance Comparison
Capacitance Comparison
Worst Best 1.16
Worst Best 1.11
Worst (125?C, 0.9V)
Worst (125?C, 0.9V)
Best (-40?C, 1.1V)
Best (-40?C, 1.1V)
Using OSTRICH from CADENCE
13
BEOL Guardband Star-RCXT

• Resistance worst case is 1.17X greater than best
• Major parameter Temperature
• Capacitance worst case is 1.13X greater than
  best
• Major parameter Process

Resistance Comparison
Capacitance Comparison
Worst Best 1.17
Worst Best 1.13
Worst (125?C, 0.9V)
Worst (125?C, 0.9V)
Best (-40?C, 1.1V)
Best (-40?C, 1.1V)
Using Star-RCXT from SYNOPSYS
14
BEOL Guardband Reduction
Best STAR-RCXT BEST SOCE
Resistance 1 (1.13 - 1) ? (x / 200) 1 (1.11 - 1) ? (x / 200)
Capacitance 1 (1.17 - 1) ? (x / 200) 1 (1.16 - 1) ? (x / 200)
Worst STAR-RCXT Worst SOCE
Resistance 1 - (1 - 1 / 1.13) ? (x / 200) 1 (1.11 - 1) ? (x/200)
Capacitance 1 - (1 1 / 1.17) ? (x / 200) 1 (1.16 - 1) ? (x / 200)
15
Outline

• Motivations
• Background
• Model Guardband Reduction
• Design Flow Test Cases
• Experimental Results
• Discussion Impact on Yield
• Conclusion

16
Design Flow
Cadence SOC Encounter
Cadence RTL Compiler
Timing Optimization
Synthesis
Synopsys DFT Compiler
Yes
Setup?
Scan Insertion
No
Cadence SOC Encounter
Cadence SOC Encounter
Floorplan
Routing
Cadence SOC Encounter
Placement
Timing Optimization
Cadence SOC Encounter
Yes
Setup
Timing Optimization
No
Yes
Setup?
Yes
Hold
No
Cadence SOC Encounter
No
CTS
Signoff
Synopsys STAR-RCXT, PrimeTime
17
Testcases and Figures of Merit

• Testcases
• Metrics
• Quality of Results
• Area, Instances, Wirelength, etc.
• Design Cycle
• Runtime, violations, TNS, WNS, etc.

Category Items
Design Jpeg, Aes, 5xJpeg
Guardband Reduction 0, 10, 20, 30, 40, 50
Technology 90nm, 65nm
Timing Mode Function, Scan
Timing Check Worst/Best, Setup/Hold
18
Outline

• Motivations
• Background
• Model Guardband Reduction
• Design Flow Test Cases
• Experimental Results
• Discussion Impact on Yield
• Conclusion

19
BEOL Guardband vs. FEOL Guardband (1)

• FEOL Guardband is much larger than BEOLs
• FEOL Worst Case Delay 2 x Best Case Delay
• BEOL Worst Cap. (1.111.13) x Best Cap.

Valuebest
Valueworst
0
100
200
Example 50 guardband reduction on FEOL Worst
case delay will be reduced by about 25
Valuebest
Valueworst
0
106
100
Example 50 guardband reduction on BEOL Worst
case capacitance will be reduced by less than 2
20
Impact of Guardband Reduction
Case GB reduction Timing corner Total path delay (ns) Average Stage delay (ns)
- 0 Worst 3.520 0.147
- 0 Best 1.435 0.060
FEOL 10 Worst 3.406 0.142
FEOL 10 Best 1.525 0.064
FEOL 40 Worst 3.069 0.128
FEOL 40 Best 1.813 0.076
FEOL 50 Worst 2.960 0.123
FEOL 50 Best 1.910 0.080
BEOL 10 Worst 3.515 0.146
BEOL 10 Best 1.437 0.060
BEOL 40 Worst 3.502 0.146
BEOL 40 Best 1.443 0.060
BEOL 50 Worst 3.497 0.146
BEOL 50 Best 1.445 0.060
FEOL BEOL 10 Worst 3.410 0.142
FEOL BEOL 10 Best 1.523 0.063
FEOL BEOL 40 Worst 3.085 0.129
FEOL BEOL 40 Best 1.804 0.075
FEOL BEOL 50 Worst 2.979 0.124
FEOL BEOL 50 Best 1.899 0.079

• FEOL
• Reducing guardband greatly affects the stage
  delay and the timing gap between best and worst
• BEOL
• Reducing guardband would not affect timing much
• From these observations, we can conclude FEOL
  will have more impacts on design outcomes.

21
Impact on Quality of Results (1) Area
BEOL only
FEOL only
FEOLBEOL

• 40 of GB Reduction

AREA FEOL BEOL FEOLBEOL
Average Reduction 13 2 13
Maximum Reduction 17 6 18
22
Impact on Quality of Results (2) Wirelength
BEOL only
FEOL only
FEOLBEOL

• 40 of GB Reduction

Wirelength FEOL BEOL FEOLBEOL
Average Reduction 12 2 12
Maximum Reduction 18 7 21
23
Impact on Design Cycle Time

• Total design cycle time f(runtime, iteration)
• Iteration depends on the timing characteristics
• Violations
• How many paths designer should concern
• Total negative slack (TNS)
• How much effort of timing optimization will be
  required
• Worst negative slack (WNS)
• Feasibility of timing convergence

24
Impact on Design Cycle Time (1) Runtime
BEOL only
FEOL only
FEOLBEOL

• 40 of GB Reduction

Runtime FEOL BEOL FEOLBEOL
Average Reduction 28 2 28
Maximum Reduction 44 15 41
25
Impact on Design Cycle Time (2) Violations
BEOL only (90nm jpeg)
FEOL only (90nm jpeg)
(90nm Jpeg case)
(90nm Jpeg case)

• 40 of GB Reduction

FEOLBEOL (90nm jpeg)
(90nm Jpeg case)
Reduction of T.V. FEOL FEOL BEOL BEOL FEOL BEOL FEOL BEOL
Reduction of T.V. Setup Hold Setup Hold Setup Hold
Violation 100 91 6 0 100 90
WNS 100 77 10 -2 100 76
TNS 100 99 22 0 100 99
26
Outline

• Motivations
• Background
• Model Guardband Reduction
• Design Flow Test Cases
• Experimental Results
• Discussion Impact on Yield
• Conclusion

27
Impact on Random Defect Yield

• Overall yield is defined by
• Random Defect Yield
• Strong function of die area (A)

Binomial Probabilistic Distribution Function
for good die
28
Impact on Parametric Yield

• Parametric Yield vs. Guardband
• Ys can be estimated by considering normal
  distribution with best case and worst case being
  set at -3s and 3s
• For x of guardband reduction, Ys is defined as,
• For 0 guardband reduction Ys0.9973
• For 40 guardband reduction Ys0.9281

about 7 yield loss
29
Impact on Yield Scenario 1

• Scenario1 Parametric yield is constant
• Adopting manufacturing-aware techniques (i.e.,
  iso-dense timing analysis, better process
  equipments, etc.) ? foundries can reduce design
  guardband
• 40 guardband reduction results in 10 increase
  in total number of good dies

_at_ aInf., d0.2/um2, 300mm wafer
RGB Originaldie area (cm2) logic area(cm2) logic area reduction die area after RGB (cm2) Ys(3 sigma) Yr Y Gross die/wafer Gooddie/wafer
0 0.850 0.480 1.000 0.850 0.997 0.844 0.841 759 639
10 0.850 0.480 0.936 0.819 0.997 0.849 0.847 789 668
20 0.850 0.480 0.912 0.808 0.997 0.851 0.849 801 680
30 0.850 0.480 0.895 0.800 0.997 0.852 0.850 809 688
40 0.850 0.480 0.869 0.787 0.997 0.854 0.852 823 701
50 0.850 0.480 0.850 0.778 0.997 0.856 0.854 833 711
30
Impact on Yield Scenario 2

• Scenario 2 Guardband reduction in design process
  (Actual guardband of fabrication is unchanged)
• Parametric yield will decrease
• Random defect yield will increase
• 20 guardband reduction results in 4 increase in
  total number of good dies per wafer

31
Conclusions

• We quantify impact of guardband reduction
• Typical outcome 13,12 and 28 reductions in
  standard-cell area, total wirelength and SPR
  runtime metrics from 40 reduction in library
  model guardband
• 100 reduction in number of timing violations for
  a netlist that is synthesized with original
  library and extraction guardbands ? this
  improvement can be very significant in improving
  timing closure and design cycle turnaround time
• 4 increase in the number of good dies per wafer
  by 20 artificial reduction from 3sigma guardband
• Our results suggest that there is justification
  for the design, EDA and process communities to
  enable guardband reduction as an economic
  incentive for manufacturing-friendly design
  practices