You might be an engineer if:

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• You might be an engineer if
• in college you thought Spring Break was metal
  fatigue failure
• you can type 70 words per minute but cant read
  your own handwriting
• you comment to your wife that her straight hair
  looks nice and parallel

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CSE 502NFundamentals of Computer Science

• Fall 2004
• Lecture 21
• Combinational Logic Circuits

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Combinational Circuits

• In combinational circuits, there is no way for a
  signal to flow from a gate output to one of its
  inputs.
• so, outputs depend only on current input values
  (not past)

• non-combinational circuits use feedback to
  implement storage
• Combinational circuits are essential building
  blocks.
• Each output of a combinational circuit is a
  function of the input values.
• each output can be specified by a truth table or
  Boolean exp.
• analysis circuit ? specification
• synthesis specification ? circuit

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Hierarchical Design

• Complex systems are designed by assembling
  simpler parts in a systematic and (usually)
  hierarchical way.
• complex function at top of hierarchy, simple
  gates at bottom
• design process can be top-down or bottom-up
• Key concept is composition of simpler circuit
  blocks to produce more complex blocks.

odd(X0,X1,X2) odd(X0,odd(X1,X2))
Z0odd(X0,,X8)
odd(X0,X1) nand(nand(X0,nand(X0,X1)),
nand(X1,nand(X0,X1)))
odd(X0,,X8)odd(odd(X0,X1,X2),
odd(X3,X4,X5),odd(X6,X7,X8))
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Design Concepts

• Hierarchical design is essential for managing
  complexity allows us to understand larger
  circuits.
• Design re-use is a key tool for reducing design
  effort.
• apply common building blocks (functional blocks)
  to construct larger systems
• large designs may contain many instances of a
  given block
• generic design elements implement common
  functions but may differ based on parameter
  values
• e.g. an odd function block, with number of inputs
  as a parameter
• Top-down design, goes from high level
  specification to simpler components using
  iterative refinement.
• In bottom-up design, we identify construct
  common elements that can be re-used multiple
  times.

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Analyzing Combinational Circuits

• Purpose of analysis is to determine what a
  circuit does.
• Procedure
• 1. verify that circuit is combinational
• 2. label all inputs, outputs and internal nets
• 3. write logic equations for internal nets in
  terms of inputs
• 4. write logic equations for outputs in terms of
  inputs
• and simplify

T2A?B
T1B ?C
T3AT1AB ?C
T4T2?DA?B ?D
F1T3T4 AB ?CB ?D BD ?
F2T2DA?BD
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Derivation of Truth Tables

• Can derive truth tables directly from circuit.
• Procedure
• 1. For n input circuit, truth table has 2n rows,
  one for each binary number from 0 to 2n-1.
• 2. Label internal nets and place columns in truth
  table for internal nets and outputs.
• 3. Fill in columns for internal nets and outputs.

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Designing Combinational Circuits

• Procedure
• 1. Determine number of inputs and outputs and
  assign a symbol to each.
• 2. Derive truth table for each output.
• 3. Obtain Boolean expressions for each output.
• 4. Create an appropriate logic diagram.
• 5. Verify correctness by analysis and/or
  simulation.
• Example design circuit with 3 inputs, 1 output
  the output should be 1 when the binary value of
  the inputs is

F X ?Y ?X ?Z ?
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Decoders

• A binary-to-unary decoder converts a binary input
  value with n bits to one of 2n possible output
  values.

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Decoder Schematic Simulation
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Encoders

• A unary-to-binary encoder converts one of 2n
  input values to an encoded binary value.

A1D2D3 A0D1D3

• A priority encoder converts the first of 2n input
  values that are 1 to the corresponding encoded
  binary value.

A1D3D2A0D 3D2?D1V D3D2D1D0 -- valid
output
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Multiplexers

• A multiplexer (a.k.a. data selector) has n
  control inputs, 2n data inputs a single data
  output
• control input value connects one data input to
  output
• circuit similar to decoder
• optional enable input allows construction of
  larger muxes
• implement with AND at output
• alternative implementation usestransmission gates

Example when S 101 Y D5
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Demultiplexers

• A demultiplexer has n control inputs, 2n data
  outputs a single data input
• control input value connects data input to one of
  the outputs

• Mux demux can be used to transmit several low
  speed signals on a single wire.

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Half-Adders

• Half-adders add two binary inputs and produce two
  binary outputs
• Ai is the input bit
• Cin is the input carry bit
• Si is the output sum bit
• Cout is the output carry bit
• Half-adders can be used to construct simple
  increment circuits

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Increment Circuit using Half Adders

• An increment circuit with n inputs and n1
  outputs computes binary value that is one larger
  than its input.

• It can be implemented using n linked half-adder
  circuits.
• to obtain a selectable incrementer replace the
  constant 1 input with a control input
• time for increment growswith number of bits
• time to compute MSB isequal to n tAND

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Full Adders

• Full adders add three binary inputs and produce
  two binary outputs
• A B are input bits
• Cin is the input carry bit
• S is the output sum bit
• Cout is the output carry bit
• Two half-adders can be used to implement a full
  adder
• Full adders can be used to implement adder
  circuits

CoutABBCinACin
SA?B?Cin
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Addition Circuit using Full Adders

• Addition circuit with 2n inputs n1 outputs
  computes the binary sum of two input values
• It can be implemented using n linked full-adder
  circuits.
• This addition circuit is called a ripple carry
  adder
• the carry-out of stage i is the carry-in of stage
  i1
• require 2 gate delays to generate each carry out
• takes time proportional to n to add two n bit
  numbers

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Simulation of Adder Circuit
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Incrementer with Carry Look-ahead

• Can speed up incrementer using carry lookahead.
• Compute carry out of each position directly from
  inputs.
• redundant AND operations, but faster
• Speed comparison
• assumptions 2 input gate has 1 ns delay, 3
  or 4 input gate has 2 ns delay, 5 to 8
  input gate has 3 ns delay, . . .
• 64 bit ripple carry incrementer needs 64 ns in
  worst-case
• 64 bit carry-lookahead incrementer needs 7 ns in
  worst-case
• So, whats the catch?
• carry lookahead uses 2000 simple gate
  equivalents
• inputs must drive many gates

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More Scalable Carry Lookahead

• 64 bit version has 7 ns delay, about 380 gates
  for carry, fanout6.

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Carry Lookahead Adder

• Ripple carry adder is too slow for fast addition
  of large values (typical computer uses 32 or 64
  bit arithmetic).
• To get a faster circuit, replace long carry chain
  with a shorter circuit. First separate carry
  logic in FA.

Let Gi be generate signal for bit i, Pi be
propagate signal and Ci be carry into bit
i. C2G1C1P1G1G0P1C0P0P1 and C3G2C2P2
G2(G1G0P1C0P0P1)P2 G2G1P2G0P1P2C0P
0P1P2 and so forth.
generate
propagate

• So high order carries can be generated with low
  delay, at the cost of more gates.

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Simulation of Carry Lookahead Adder
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More Scalable Lookahead Adder

• A more scalable lookahead adder can be obtained
  by writing the logic equations differently.
• Let G(i,j) be true if a carry is generated from
  within the bits i-j1 up to i G(i,j)Gi Gi-1Pi
  ??? Gi-j1Pi-j2???Pi
• Let P(i,j)Pi???Pi-j1.
• Now, we can also write,
• G(i,1)Gi P(i,1)Pi
• G(i,2)G(i,1)G(i-1,1)P(i,1) P(i,2)P(i,1)P(i-1,
  1)
• G(i,4)G(i,2)G(i-2,2)P(i,2) P(i,4)P(i,2)P(i-2,
  2)
• G(i,8)G(i,4)G(i-4,4)P(i,4) P(i,8)P(i,4)P(i-4,
  4)
• These equations lead directly to the design on
  the following page.

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Lookahead Adder Schematic
Up to 22log2n gate delays.
Partial full adder
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Adder-Subtracter

• For 2s compliment numbers, implement subtraction
  (A B) by taking the compliment of the
  subtrahend and adding to the minuend (A B? 1)
• When sub0, result is AB.
• When sub1
• bit flipper complements all bits of B
• adder sums and adds 1A-B A (-B) A
  (not(B) 1) A not(B) 1
• Takes just slightly more time than plain adder.

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Simulation of 4 Bit ALU

• if S0 then DB-A
• if S1 then DA-B
• if S2 then DAB
• if S3 then D-A

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4 Bit ALU Design Elements
Negate
4 Bit Adder
Negate
Negate
4 Bit Adder
4 Bit Adder
Quad 41 Multiplexor