Brief Introduction to Verilog

1
Brief Introduction to Verilog

• Weiping Shi

2
What is Verilog?

• It is a hardware description language
• Allows designers to quickly create and debug
  large scale designs
• Similar to C in syntax
• Verilog will be used to do design assignments in
  this course

3
Sample Half Adder

• module Add_half (sum, c_out, a, b)
• input a, b
• output sum, c_out
• wire c_out_bar
• xor (sum, a, b)
• nand (c_out_bar, a, b)
• not (c_out, c_out_bar)
• endmodule

4
Module Hierarchy

• Modules can be instantiated within other modules
• Allows for simplicity and regularity in the
  design
• Example Use two half adders to create a full
  adder

5
Module Hierarchy Example

• module Add_half ( sum, c_out, a, b )
• input a, b
• output sum, c_out
• wire c_out_bar
• xor (sum, a, b)
• nand (c_out_bar, a, b)
• not (c_out, c_out_bar)
• endmodule
• Module Add_full ( sum, c_out, a, b, c_in ) //
  parent module
• input a, b, c_in
• output c_out, sum
• wire w1, w2, w3
• Add_half M1 ( w1, w2, a, b )
• Add_half M2 ( sum, w3, w1, c_in ) // child
  module
• or ( c_out, w2, w3 ) // primitive
  instantiation
• endmodule

6
Alternative Half Adders

• module Add_half ( sum, c_out, a, b )
• input a, b
• output sum, c_out
• assign c_out, sum a b // Continuous
  assignment
• endmodule
• module Add_half (sum, c_out, a, b )
• input a, b
• output sum, c_out
• reg sum, c_out
• always _at_ ( a or b)
• begin
• sum a b
• c_out a b
• end
• endmodule

7
Structural v.s. Behavioral

• Verilog can be structural or behavioral
• Structural definition specifies the gates and
  their connections explicitly
• Behavioral definition specifies the functionality
  of a design
• Does not contain any structural information such
  as transistors or gates
• Logic synthesis software implements the structural

8
Behavioral Example2 Bit Comparator

• module comparator (a_greater, b_greater, equal,
  a, b)
• input a, b
• output a_greater, b_greater, equal
• reg a_greater, b_greater, equal
• always _at_(a or b) // either a or b changes
• begin
• if (a b)
• begin
• a_greater 1
• b_greater 0
• equal 0
• end
• if (a
• begin
• a_greater 0
• b_greater 1
• equal 0
• end
• if (ab)

9
Alternate comparator

• module comparator (a_greater, b_greater, equal,
  a, b)
• input a, b
• output a_greater, b_greater, equal
• assign a_greater (a b) ? 1 0
• assign b_greater (a
• assign equal (ab) ? 1 0
• endmodule
• Uses a conditional continuous assignment to set
  the outputs.

10
Clarification

• Registers are used when an output is updated on
  an event. The value must be held until a new
  event updates that value.
• Assign statements are used when the output is
  continuously being assigned.

11
Using Verilog on Sun

• Create your Verilog module in a text file
  entitled
• vi filename.v
• Compile the file using the command
• verilog filename.v

12
Testbench

• Manipulate the module inputs to observe the
  circuit reaction
• Uses module hierarchy
• Introduces the concept of delay

13
Sample Testbench for a Half Adder

• module tbench
• reg a,b // regs connect to module inputs
• wire sum,cout // wires connect to module
  outputs
• half_adder M1(cout,sum,a,b) // instantiate the
  half adder
• initial
• begin
• a 0, b 0 //time 0
• 5 a 1, b 0 //time 5
• 3 a 1, b 1 //time 8
• 4 a 0, b 1 //time 12
• 52 a 0, b 0 //time 64
• 70 finish //stops the simulation
• end
• initial
• begin
• monitor(time,a b, bb coutb
  sumb,a,b,cout,sum)//displays the variable
  values at each
• //unit of time that an event occurs

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Testbench Results

• Compiling source file "ha.v"
• Compiling source file "tbench.v"
• Highest level modules
• tbench
• 0a 0, b0 cout0 sum0
• 5a 1, b0 cout0 sum1
• 8a 1, b1 cout1 sum0
• 12a 0, b1 cout0 sum1
• 64a 0, b0 cout0 sum0
• "tbench.v" finish at simulation time 134

15
Arrays

• Arrays can be expressed in Verilog
• Can be used for inputs, outputs, wires, regs,
• Ex 4 bit input
• input 30 A

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Array Example

• module xor_demo(xor_group,xor_bit,A,B)
• input 30 A, B
• output 30 xor_group,xor_bit
• assign xor_group A B
• assign xor_bit0 A0 B0
• assign xor_bit1 A1 B1
• assign xor_bit2 A2 B2
• assign xor_bit3 A3 B3
• endmodule

17
Array Test bench

• module tbench
• reg 30 A, B
• wire 30 xor_group,xor_bit
• xor_demo M1(xor_group,xor_bit,A,B)
• initial begin
• A 0 B 0
• 5 A 4'b0001 B 4'b1100
• 10 A 4'd5 B 4'd10
• 5 A 4'hF B4'hE
• end
• initial begin
• 40 finish
• end
• initial begin
• monitor(time,"Ab Bb groupb
  bitb",A,B,xor_group,xor_bit)

18
Xor Array Results

• Compiling source file "xor.v"
• Compiling source file "xtbench.v"
• Highest level modules
• tbench
• 0A0000 B0000 group0000
  bit0000
• 5A0001 B1100 group1101
  bit1101
• 15A0101 B1010 group1111
  bit1111
• 20A1111 B1110 group0001
  bit0001
• L18 "xtbench.v" finish at simulation time 40

19
Parameters

• Parameters can be used to name integers
• Parameter declaration is done when you define the
  port list
• Ex parameter true 1b1
• parameter false 1b0
• parameter stop 5h1F

20
FSM Example Car
accelerator
brake
speed
clock
21
Behavioral Description

• module car(speed, a, b, clock)
• input a, b, clock
• output 10 speed
• reg 10 speed
• parameter stopped 2b00
• parameter fast 2b11
• always _at_(posedge clock or b)
• begin
• if (b 1 speed ! stopped)
• speed speed 1
• else if (b 0 a 1 speed ! fast)
• speed speed 1
• end
• endmodule