A Method to Decompose MultipleOutput Logic Functions

1
A Method to Decompose Multiple-Output Logic
Functions

• Tsutomu Sasao
• Munehiro Matsuura

2
Outline of the Talk

• Background
• Decomposition of Logic functions
• A New Method to Decompose Multiple-output
  Functions
• Example
• Experimental Results
• Conclusions

3
Decomposition of Logic Functions

• Useful in the design of FPGAs andLUT cascades.
• A method to implement multiple-output functions
  is needed.

4
Decomposition for Multiple-Output Functions

• Existing methods
• MTBDDs(Multi-Terminal Binary Decision Diagrams)
• Hyper functions
• ECFNs (Encoded Characteristic Functionsfor
  Non-zero outputs)
• Method in this work
• Characteristic functions of multiple-output
  function

5
Decomposition of Single Output Functions
Decomposition Chart
X1(x1, x2)
Bound set
00
01
10
11
x1
H
X1
G
00
0
1
0
1
x2
Free set
f
01
1
1
1
1
x3
X2(x3, x4)
x4
X2
10
1
0
1
0
11
1
0
1
0
f g(h(X1),X2)
Column multiplicity m2
6
Functional Decomposition Using BDDs
X1
Column Multiplicity Width of BDD in X1 The
number of nodes in X2 that are directly
connected to nodes in X1.
X2
0
1
7
Functional Decomposition Using BDDs
x1
x1
x2
x2
x2
x2
x3, x4
x3
x3
0
1
00
1
1
01
x4
1
0
10
1
0
11
0
1
0 edge
1 edge
8
LUT Cascade
Cells
Rails
9
Design Method of an LUT Cascade Using a BDD
k
k
k
0
1
0
1
0
1
10
Decomposition of Multiple-Output Functions

• For m-output functions, MTBDDsoften have 2m
  terminal nodes.
• In many cases, the column multiplicityis too
  large.

• Solution
• Use a BDD-for-characteristic-function approach.

11
Characteristic Function
Multiple-output function F(f0(X), f 1(X),,
fm-1(X))
Characteristic function
12
Example of a Characteristic Function
x1
x2
f
x2
y
x1
c
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
1
1
1
13
BDD for Characteristic Function (BDD-for-CF)
a0
Two-bit adder
b0
b0
a1 a0
s0
s0
s0
0
0
b1 b0
)
0
a1
a1
s2 s1 s0
b1
b1
b1
b1
s1
s1
s1
s1
s2
s2
0
1
0
0
14
Theorem

• Let the variable ordering of BDD for CF be
  (X1, Y1, X2, Y2), and let W be the width of the
  BDD , where edges to constant 0 from the output
  variables are ignored.
• Then

15
Functional Decomposition with Intermediate Outputs
H
Y1
X1
G
Y2
X2
16
LUT Cascade with Intermediate Outputs
17
Decomposition Using BDD-for- CFs
Two-bit adder
a0
a1 a0
b0
b0
b1 b0
)
s0
s0
s0
s2 s1 s0
a1
a1
b1
b1
b1
b1
s1
s1
s1
s1
s2
s2
1
18
Two-bit Adder
a1
a1
b1
b1
b1
b1
a0
b0
s1
s1
s1
s1
s2
s2
1
19
Two-bit Adder
a0
a0
b0
u0
b0
b0
0
0
0
0
1
0
1
0
0
a1
a1
0
1
1
1
1
b1
b1
b1
b1
s1
s1
s1
s1
s2
s2
1
20
Two-bit Adder
a1
a1
b1
b1
b1
b1
s1
s1
s1
s1
s2
s2
1
21
Two-bit Adder
a1
b1
s1
u0
s2
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
1
0
1
a1
a1
0
1
1
1
0
1
0
1
1
0
b1
b1
b1
b1
1
1
1
1
1
s1
s1
s1
s1
a1
b1
u0
s2
s2
1
s1
s2
22
Two-bit Adder

• Two bit adder

a1 a0
b1 b0
)
s2 s1 s0
Number of LUT outputs 4
Number of cells 2
23
Experimental Results
24
RGB Color Converter

• U-0.169R-0.3316G0.5B
• Inputs 8 bits x 3 24 bits
• Outputs 8 bits Sign bit9 bits

3
5
13
4
10
8
8
9
25
RGB Color Converter

• LUT Cascade
• 35 13-input LUTs, 4 level
• FPGA designed by SynplifyISE
• 12818 4-input LUTs
• 78.7ns, Xilinx Virtex XCV600-6 (316 pins)

26
Binary to BCD Converter

• Inputs 16 bits
• Outputs 4 bit x 5 digits20 bits

x1
x12
x13
x14
x15
x16
x11

7
10

f1
f2
f3
f4
f5
f6
f7
f19
27
Binary to BCD Converter

• LUT Cascade
• 36 11-input LUTs, 3 levels
• FPGAdesigned by SynpfilyISE
• 695 4-input LUTs, 70.7 ns (Verilog)
• 1659 4-input LUTs, 33.1ns (BDD)
• Xilinx Virtex XCV150-6 (260 pins)

28
Q. and A.

• Reviewers Comment
• The method is only useful for the design of
  ripple-carry adder like circuits.

Our answer This method found a cascade
structure that is hard to find by a conventional
approach.
29
C432 Reverse Engineered by J. P. Hayes
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
30
C432

• 27-Channel Interrupt Controller
• 36 Inputs, 7 Outputs, 160 Gates

6
14
8
8
7
8
7
31
Summary
Functional decompositions with intermediate
outputs using BDDs-for-CF

• Is useful for the design of LUTcascades with
  intermediate outputs.
• Often finds faster circuits than FPGAs.
• Can find structures that are easyto layout.