Next Generation Network Processor

1
Next Generation Network Processor Development
Tools

• YS Kim
• Field Application Engineer
• Sep 2002

2
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

3
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

4
Intels 4 Strategic Architectures
5
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

6
What is a Network Processor?

• Flexible Programming Capability
• Minimal fixed format packet/cell states between
  processing stages
• Software controlled state maintenance
  manipulation
• Performance capable of deep packet/cell
  inspection at wire rates
• Highly integrated Processor
• Includes memory controllers
• Packet / cell dataplane I/O
• Fabric interface controllers
• Optionally, control plane interface e.g. PCI

7
Sophisticated Packet Analysis
Ethernet Preamble

• New tasks require looking deeper into the packet

Destination MAC Address
Ethernet Header

• Ethernet Switching
• Simple Quality of Service
• 802.1p Q (Type of Service)
• Routing (IP Forwarding)
• Advanced QoS
• TCP Port Number Filtering
• Allow ftp, filter http
• Security
• Stateful Inspection of all of the above

• Ethernet Switching

• Ethernet Switching
• Simple Quality of Service
• 802.1p Q (Type of Service)
• Routing (IP Forwarding)

• Ethernet Switching
• Simple Quality of Service
• 802.1p Q (Type of Service)

• Ethernet Switching
• Simple Quality of Service
• 802.1p Q (Type of Service)
• Routing (IP Forwarding)
• Advanced QoS
• TCP Port Number Filtering
• Allow ftp, filter http

Source MAC Address
Length or Type
IP Header
Source TCP Port
TCP Header
8
How the Network Processor Processing Packets
9
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

10
What is the IXP1200?

• Offers the best of ASICs RISC Processors
• Dedicated, programmable network processor engines
• Integrated RISC CPU core for mgmt control
• Unmatched combination of performance,
  flexibility, and opportunity for differentiation
• Centerpiece of the Internet Exchange Family
• Providing intelligence in the fast-path of
  network traffic processing
• Hardware, software, and development environment
  to create a total solution

11
IXP1200 NP enables flexible product development

• Very Low Power Parallel Processor Architecture
  with 7 232 MHz RISC processors
• Hardware Based Multithreading on 6 RISC engines -
  Cost Effective
• Distributed Data Storage Arch Supports Very
  Simple Programming Model
• Active Memory Optimizations - High Performance
  With Commodity RAMs
• Scalable Architecture

12
IXP1200 Block Diagram
13
IXP1200 Features

• Microengines Processor
• 232 MHz
• 6 Microengines
• 2K control store on all uEng.
• SRAM Interface
• 32-Bit _at_ 116 MHz
• Slow Side Ready Signal
• 8 MB Max
• SDRAM Interface
• 64-Bit _at_ 116 MHz
• 256 MB Max
• IX Bus Interface
• 85 MHz (multiple loads)
• 104 MHz Point-to-Point
• Rosetta FPGA for Utopia 2, 3 interface
• PCI Interface
• 32-Bit _at_ 66 MHz

Applications CPU (Optional)
PCI Bus
IXP1200 Network Processor
SRAM
SDRAM
Flash
IX Bus
Fast / Gigabit Ethernet MACs
Fabric I/F FPGA
Full Utopia 2, 3 Interface
14
IXP1200 Target Applications

• Multi Service Switches
• Voice over IP blades
• DSLAMs
• VPN Gateways
• 3G Base Station transceivers

15
Intel IXDP1200 Advanced Development Platform
16
IXDP1200 Platform Features

• Consists of four sub-systems
• IXM1200 Network Processor Base Card
• IXD4501 LAN I/O Option Card
• IXD4521 WAN I/O Option Card
• Each Option Card attaches to IXM1200 (1 Option
  Card per Base Card))
• Eight slot 6U CompactPCI Chassis
• Includes ESC3306 System Controller
• Integrated with the Network Processor Software
  Developers Kit (IXA SDK)

17
IXA Software Development Kit

• Pre-installed on the IXDP1200 Advance Development
  Platform
• Diagnostics
• VxWorks
• Tornado 2
• IXA SDK Volume I
• Windows NT Integrated Development Environment /
  Example Code
• Software development environment for the IXP1200
  Network Processor Family
• Extensive software library building blocks
  example designs
• Quickly build custom network processor-based
  applications with value-added features
• Accelerates customers Time-To-Market
• Reduced development costs
• Increases product life cycle
• Other marks and brands may be claimed
  as the property of others

18
IXA SDK 2.0 Development Advantage

• IXA SDK 2.0 New Features
• Enhanced Workbench / Transactor - advanced
  graphical simulation, profiling and debugging IDE
• Enables faster prototyping, intuitive
  optimization, supports data plane and control
  plane applications
• Full support for choice of popular Linux or
  VxWorks operating systems
• Choice of leading embedded OS platforms
• Advanced High Level Programming Framework (ACE)
  and infrastructure software
• Enables development of modular, portable code
  blocks or integration of 3rd party software
  products for longer product life, easier
  modifications.
• Eliminates time consuming development of crucial
  infrastructure software
• Advanced Development tools Microengine C
  Compiler and Embedded Linux IDE
• High level programming and debugging tools easing
  development for the IXP1200 Micoengines and
  StrongARM Core
• Suite of example applications and software
• Speeds development of with provided common
  networking building blocks
• Other marks and brands maybe claimed as the
  property of others

19
ATM/OC-3 to Fast Ethernet IP Router Example
Design

• Runs on the IXDP1200 Advanced Development
  Platform
• Demonstrates full duplex ATM-Ethernet protocol
  conversion over dual OC-3 links.
• Supports software-based Segmentation and
  Reassembly (SAR) of ATM cells
• Includes software-based Cyclic Redundancy
  Checking (CRC)
• IP over ATM encapsulation (RFC 1577)
• ATM Adaptation Layer 5 (AAL-5) processing,
  Unspecified Bit Rate (UBR) traffic

20
Microengine C language

• Programming abstraction for simplified
  Microengine coding.
• Microengine C dest (a b) - c
• Microcode alu dest1, a, , b alu
  dest2, dest1, -, c
• Microengine C and Compiler
• Subset of ANSI C language and ANSI C library
• Optimizes code for the Microengines
• Microengine C Networking Library
• Provides a library of common, portable network
  functions across Intel network processors
• Permits portability of functions across a range
  of Intel family of network processors
• Intrinsics for specialized IXP1200 functions.
• Ex move groups of data to from SDRAM
• Support for microcode (in-line assembly functions)

For Simplified, Portable, Microengine
Programming!
21
Embedded OS Support

• VxWorks support (Volume I of IXA SDK 2.0)
• 3rd party (WindRiver) supplied VxWorks
• 60 day trial version of Wind River Systems
  Tornado toolchain
• VxWorks BSPs
• Linux support (Volume II of IXA SDK 2.0)
• 3rd party (LynuxWorks) big-endian StrongARM
  Linux port.
• 60 day trial version support package from
  LynuxWorks
• Windows NT and RedHat Linux cross-development
  tools
• Linux BSPs
• Supplied system ACEs for IP stack and IXF
  hardware

22
Development Environments for VxWorks and Linux
23
IXP1200 Development Station Embedded VxWorks or
Linux (sample configuration)
Microengine Toolchain
Developers Workbench 2.0(Installed from Vol. I
or II CD)
IXM1200 Network Processor Base Card
500Mhz Pentium III System Controller (SBC)
StrongARM Toolchain
VxWorks Or Linux
Wind River Tornado 2.01 (Installed from Vol. I
CD) or GNU C/C cross compiler and Linux IDE
(optional)(Installed from Vol. II CD)
PCI
NT
Enet
Serial
IXDP1200 Advanced Development Platform
PCI-to-target not supported for Linux system
24
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

25
Intel IXA The Next Generation
Customer Applications

• Intel IXA characteristics
• Definable Intel IXA is Intels packet
  processing architecture focused on our network
  processors
• Measurable Architectural core is the
  microengine technology Intel XScale
  microarchitecture
• Lasting Software portability across multiple
  product generations

Enables softwareportability
Intel IXA portability framework
Intel IXA Network Processor
Enables low power, highdensity processing
Intel XScale microarchitecture

Microengine technology
Micro- engine
Micro- engine
Enables high-performance, programmable network
processing
26
Intel Network Processor Roadmap
Bridgton (full Duplex 192)
OC-192
IXP2800
Tiburon (integration)
S
OC-48
IXP2400
Jonesport (cost reduction)
S
IXP1200 IXP1240 IXP1250
IXP1200 C-0 step
IXP1240 IXP1250
OC-12
S
Q101
Q201
Q301
Q401
Q102
Q202
2H02
1H03
2H03
Roadmaps, dates, product features are subject
to change without notification. Other brands and
marks are the property of their respective owners.
27
IXP2400 External Features

• External Interfaces
• Interface supports UTOPIA 1/2/3, SPI-3 (POS-PL3),
  and CSIX.
• Four independent, configurable, 8-bit channels
  with the ability to aggregate channels for wider
  interfaces.
• Media interface can support channelized media on
  RX and 32-bit connect to Switch Fabric over SPI-3
  on TX (and vice versa) to support Switch Fabric
  option.
• Two Quad Data Rate SRAM channels.
• A QDR SRAM channel can interface to
  Co-Processors.
• One DDR DRAM channel.
• PCI 64/66 Host CPU interface.
• Flash and PHY Mgmt interface.
• Dedicated inter-IXP channel to communicate fabric
  flow control information from egress to ingress
  for dual chip solution.

Host CPU (Optional)
PCI 64-bit / 66 MHz
QDR SRAM 20 Gbps 32 M Byte
Classification Accelerator
IXP2400 (Receive)
CoProc Bus
DDR DRAM 2 GByte
Micro-Engine Cluster
Customer ASICs
IXP2400 (Transmit)
Flash
Slow Port
Utopia 1/2/3 or POS-PL2/3 Interface
Flow Control Bus
Utopia 1,2,3 SPI 3 (POS-PL3) CSIX
ATM / POS PHY or Ethernet MAC
Switch Fabric Port Interface
28
IXP2400 Internal Architecture
72
Stripe/byte align
MEv2 2
MEv2 1
DDRAM
Rbuf 64 _at_ 128B
S P I 3 or C S I X
32b
MEv2 3
MEv2 4
XScale Core 32K IC 32K DC
G A S K E T
Tbuf 64 _at_ 128B
PCI (64b) 66 MHz
32b
64b
MEv2 6
MEv2 5
Hash 64/48/128
Scratch 16KB
CSRs -Fast_wr -UART -Timers -GPIO -BootROM/Slow
Port
MEv2 7
MEv2 8
QDR SRAM 1
QDR SRAM 2
E/D Q
E/D Q
18
18
18
18
29
IXP2400 Internal Features

• Internal Product Capabilities
• Eight next generation Microengines (MEv2)
  operating at 600MHz with significant architecture
  enhancements such as
• Automated packet scheduling and handling to free
  MEv2 cycles for packet processing
• Local data store enables higher performance for
  structured applications
• Hardware acceleration for DiffServ, MPLS, and
  other QoS schemes
• ATM Segmentation and Reassembly (SAR) support
  with headroom.
• Intel XscaleTM microarchitecture core operating
  at 600MHz

30
Micro-engine version 2 (MEv2)

• New Features and Instructions
• Enhanced Event signaling Thread-control
• More execution resources

31
Microengine V2
From Next Neighbor
D-Push Bus
S-Push Bus
Control Store 4K Instructions
Local Memory
128 GPR
128 GPR
128 Next Neighbor
128 S Xfer In
128 D Xfer In
2 per CTX
LM Addr 1
LM Addr 0
P-Random
A_Operand
B_Operand
CRC Unit
CAM
ExecutionData path
Multiply
CRC remain
Find first bit
Add, shift, logical
Local CSRs
ALU_Out
To Next Neighbor
128 S Xfer Out
128 D Xfer Out
D-Pull Bus
S-Pull Bus
32
MEv2 new features instructions

• Local Memory
• Facilitates development and efficient execution
  of structured applications
• Refer to them via index registers similar to
  GPRs
• Holds 640 long-words
• Access latency is like registers
• Next Neighbor registers
• Facilitates efficient software pipelining and
  data transfer between MEs
• Provides register accesses of ME neighbor
• Each ME includes 128 next neighbor registers
• CRC hardware
• Accelerates ATM AAL/SAR function
• Provides crc_16, crc_32, and AAL 1/2/3/4/5
• Can optionally select the bytes to operate on

33
MEv2 new features instructions

• CAM (Content Addressable Memory)
• Improves usage of multiple threads on same data
• Result can be used to dispatch to the proper
  code. Lock can flag in-flight or changing data.
• Performs parallel look-up on 16 entries of 32-bit
  value. Reports miss, hit, or locked, along with
  the LRU or matched entry, respectively.
• Multiply hardware
• Supports metering in QoS algorithms
• DiffServ, MPLS
• Supports 16x16, 32x32
• 8 bits per instruction
• Pseudo Random Number generation
• Accelerates RED, WRED algorithms
• 64-bit Time-stamp and 16-bit Profile count

34
MEv2 Event signaling Thread-control

• Provides 8 threads Vs 4 in IXP1200
• Can configure as 8, 4 threads with entire MEv2
  resources (GPR, memory, Txfr Reg, etc).
• Each thread has its own program counter,
  registers, signal wakeup events
• Each thread uses up to 15 event signals
• DRAM SRAM transaction signals
• Next neighbor previous neighbor signals
• Inter-thread on same ME signals
• Time-stamp hitting future-count signals
• Wakeup of a thread can be based on AND or OR
  logical operation among subset or all of the 15
  signals

35
MEv2 Execution Resources

• More registers on each ME
• 256 General Purpose Registers Vs 128 in IXP1200
• 512 Transfer Registers Vs 128 in IXP1200
• ME resources divided among user defined of
  threads
• 4K-instruction Control Store Vs 2K in IXP1200

36
MEv1 Versus MEv2
37
IXP2400 Target Applications

• IXP2400 will provide IXP 1200 customers a
  performance upgrade for OC-12 applications and
  enable platforms up to OC-48.
• WAN Edge/Access Aggregation
• Includes IP Service Switches, Multiservice
  Switches, DSLAM, Cable Head End
• Wireless Infrastructure
• BSC/RNC, xGSN, PDSN, MSC
• Layer 4-7 Switches
• Includes Firewall, Server Offload, Content-Based
  Load Balancing

38
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

39
Intel Network Processor Roadmap
Bridgton (full Duplex 192)
OC-192
IXP2800
Tiburon (integration)
S
OC-48
IXP2400
Jonesport (cost reduction)
S
IXP1200 IXP1240 IXP1250
IXP1200 C-0 step
IXP1240 IXP1250
OC-12
S
Q101
Q201
Q301
Q401
Q102
Q202
2H02
1H03
2H03
Roadmaps, dates, product features are subject
to change without notification. Other brands and
marks are the property of their respective owners.
40
What is IXP2800?

• Single chip OC-192 / 10 GbE network processor
  that combines Layer 3 / 4 forwarding and traffic
  management functions at wire rate
• Fully software programmable store and forward
  architecture
• Industry standards interfaces to memory
  subsystems, media and switch fabrics
• Does not require specialized classification
  coprocessor or traffic manager
• Only Intel delivers
• Intel silicon technology drives performance and
  volume
• IXA Developers Network - 3rd party hardware and
  software ecosystem
• World class development tools

41
IXP2800 highlights

• 2nd generation network processor
• 1.4 GHz operation delivers 20 Giga-operations
  per second
• 10 Gbs full duplex media interface
• 50 Gbs packet memory bandwidth
• 30 Million packets per second L4 forwarding
• 60 Million Enqueue/Dequeue operations/sec
• Advanced HW support for Queueing, Traffic
  Shaping, SARing, and policing
• 14W, 1357 BGA
• Available Q3 02

42
IXP2800 features

• (16) Multi-threaded microengines
• 8 threads per engine
• 4 K word control stores
• 1.4 GHz operating frequency
• XScale Core
• 700 MHz operating frequency
• 32 Kbytes instruction cache / 32 Kbytes data
  cache
• Media / Switch Fabric Interface
• 2 x 16 bit LVDS Transmit Receive
• Configured as CSIX or SPI-4
• Network Processor Forum proposal to become
  industry standard for fabric and media interfaces
  for 10Gbs

43
IXP2800 features cont

• PCI Interface
• 64 bit / 66 MHz interface for control
• QDR Interface (with parity)
• (4) 36 bit SRAM channels (QDR or coprocessor)
• Network Processor Forum proposed coprocessor
  Standard Interface
• Rambus DRAM Interface (w/ECC)
• (3) Independent direct Rambus DRAM interfaces
• Supports 4i banks or 16 interleaved banks
• Supports 16/32 byte bursts
• Tuned for PC800 or PC1066 RDR

44
72
72
72
IXP2800
Stripe/byte align
RDRAM 1
RDRAM 3
RDRAM 2
MEv2 2
MEv2 3
MEv2 4
MEv2 1
Rbuf 64 _at_ 128B
S P I 4 or C S I X
16b
MEv2 7
MEv2 6
MEv2 5
MEv2 8
XScale Core 32K IC 32K DC
G A S K E T
PCI (64b) 66 MHz
Tbuf 64 _at_ 128B
64b
16b
MEv2 10
MEv2 11
MEv2 12
MEv2 9
Hash 64/48/128
Scratch 16KB
MEv2 15
MEv2 14
MEv2 13
QDR SRAM 2
QDR SRAM 1
QDR SRAM 3
MEv2 16
QDR SRAM 4
CSRs -Fast_wr -UART -Timers -GPIO -BootROM/SlowPo
rt
E/D Q
E/D Q
E/D Q
E/D Q
18
18
18
18
18
18
18
18
45
Microengine version 2
D-Push Bus
S-Push Bus
From Next Neighbor
Control Store 4K Instructions
Local Memory 640 words
128 GPR
128 GPR
128 Next Neighbor
128 S Xfer In
128 D Xfer In
LM Addr 1
2 per CTX
B_op
A_op
LM Addr 0
Prev B
Prev A
P-Random
B_Operand
A_Operand
CRC Unit
Multiply
Lock 0-15
Status and LRU Logic (6-bit)
TAGs 0-15
32-bit ExecutionData Path
Find first bit
CAM
CRC remain
Add, shift, logical
Status
Entry
Local CSRs
ALU_Out
To Next Neighbor
Timers
128 S Xfer Out
128 D Xfer Out
Timestamp
D-Pull Bus
S-Pull Bus
46
IXP2800 ecosystem

• QDR suppliers - 18/36 Mb ( http//www.qdrsram.com
  )
• Micron / MT54V512H18A
• IDT / IDT71T6280H
• Cypress / CY7C1302V25
• Samsung NEC
• RDRAM suppliers - 288/576 Mb
• Samsung / 750948-001
• Elpida (NEC Hitachi)
• Toshiba
• QDR look aside coprocessor (see Intel for vendor
  contacts)
• SiberCore (Classification)
• IDT (Classification)
• Lara Networks (TCAM)
• NetLogic MicroSystems (TCAM)

47
Intel complementary technology

• SPI-4 Peripherals
• Calypso (1x10 Gb/sec Ethernet MAC) samples Q102
  from Intel OPG
• Ben Nevis (10x1Gb/sec Ethernet MAC) samples Q102
  from Intel NCD
• Calypso (OC-192 Framer, POS/ATM/Ethernet/HDLC)
  from Intel OPG
• Bachelor (4xOC-48 16xOC-12 POS Framer) Intel
  OPG
• CSIX switch fabric strategy
• Multi-vendor approach to provide customers with
  the greatest set of fabric alternatives possible
• PowerX, SiSilk, Teracross, Sandburst, Velio,
  Zettacom

48
IXP2800 target applications

• Core Applications
• Core routers

• Edge / Access Access
• Metropolitan Area Network Switches/routers
• Edge Routers
• Multi-service Switches
• Aggregation
• Security
• Content Aware L4-L7
• Wireless Infrastructure Switches/routers
• SSGN
• GGSN
• RAN

• Enterprise
• Switches/routers
• Data center / SAN

49
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

50
Intel Development Platform Roadmap
Bridgton (full Duplex 192)
Deer Island Dev. Platform
OC-192
IXP2800
Tiburon (integration)
S
Angel Island Dev. Platform
OC-48
IXP2400
IXDP1200 Development Platform
IXP12EB Evaluation Kit
Jonesport (cost reduction)
S
IXP1200 IXP1240 IXP1250
IXP1240 IXP1250
OC-12
IXP1200 Yarmouth
S
Q101
Q201
Q301
Q401
Q102
Q202
2H02
1H03
2H03
Roadmaps, dates, product features are subject
to change without notification. Other brands and
marks are the property of their respective owners.
51
Table of Baseboards and Media Cards
52
Development Platform Components
Modular Media Card
Chassis
Baseboard


Battery Drew Cross Island No Media Card
Kent Island Cranberry Island Eagle Island

Baffin Island
53
IXA Software Development Kits (SDK) Roadmap
Pt. Reyes IXA SDK 3.1
IXA SDK 3.0 (IXP2400/ IXP2800)
IXP2800
IXP2400
SDK 2.01(patchrelease)
CalaverasIXA SDK 2.1
IXA SDK2.0
IXA SDK1.3
IXP1200IXP1240IXP1250
Q101
Q201
Q301
Q401
Q102
Q202
Q302
Q402
Q103
Roadmaps, dates, product features are subject
to change without notification. Other brands and
marks are the property of their respective owners.
54
Simulation / Development Environment
Workbench GUI Editor, Debugger,
XScale Development
MEv2 Development
Serial/Ethernet/PCI/JTAG connection
Assembler
Assembler
Linker
Linker
C/C Compiler
uC Compiler
Object
Std Debug
Object
Std Debug
MEv2 Simulation
Hardware Debug Environment
Transactor
Hardware Debug Libraries Loader, Debug, etc. (BSP
Specific)
Foreign Model Interface
Peripheral Models
IXP Evaluation Boards ACPP Boards OEM Boards
55
XScale Development Tools

• Supplied by 3rd parties
• Leveraging existing tools and vendors widely
  accepted in the industry
• Optimized for XScale Microarchitecture
• Cross-development tools for VxWorks
• Windows hosted Tornado toolchain from WindRiver
• Graphical IDE
• Cross-development tools for embedded Linux
• Red Hat Linux and Windows hosted GNUPro toolchain
• Provide following capabilities cross-compiling,
  linking, source-level debugging on the target
• Build kernel, kernel drivers, user applications
  and flash image

56
Production Building Blocks

• Ipv4 L3 Forwarding (RFC1812 compliant)
• Queue Manager
• Transmit Scheduler
• Interfaces (Transmit and Receive)
• Vallejo Quad GbE
• Ben Nevis 10x1 GbE
• Calypso OC-192 POS/Ethernet
• IXF6048 OC48 POS
• IXF6048 Quad OC12 ATM
• Control Plane
• TCP/IP Stack interface
• Route Cache Manager
• Implemented as microblocks and core components

57
Applications

• Demonstrate how to use production building blocks
• Applications will be available for both IXP2800
  and IXP2400
• Ethernet
• Packet over SONET
• ATM
• Each application includes the following functions
• Packet assembly
• Flow and multi-field classification
• IP verify and forwarding
• Metering
• Congestion avoidance (RED and WRED)
• Queue management
• Transmit Scheduling (Strict priority, WRR, DRR,
  and WFQ)

58
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

59
IXP2400 Full-Duplex OC-48 System Implementation
S D R A M
DDR SDRAM Packet Memory
QDR SRAM Queues Tables
QDR
QDR
Host CPU (IOP or iA)
T C A M
ClassificationAccelerator
IXP2400 Receive Processor
IXF6048 Framer
SwitchFabricGasket
OC-48
OC48
OC48
OC48
IXP2400 Transmit Processor
1x OC-48 or4x OC-12
T C A M
ClassificationAccelerator
S D R A M
Q DR
DDR SDRAM Packet Memory
QDR SRAM Queues Tables
QDR
60
IXP2400 Edge Multi-Service Switch - OC-48
WAN/LAN Solutions
IXP2400
Oahu Quad Gig Phy
Utopia3
Phy Interface
Amazon IXF6048 OC-48c ATM POS Framer
Vallejo 4 x 1G Ethernet MAC
1 Gig LAN or Server Farm
SPI-3 (Utopia3 Packet)
SPI-3 (Utopia3 Packet)
WAN Backbone (ATM, SONET)
Optical Ring
IXP2400
1 GigLAN Backbone or Server Farm
OR
CSIX Switch Fabric
80 Gig 1 TerabitSwitch Fabric
61
IXP2400 OC12/GbE 3G RNC Line Card
Host CPU (IOP or iA)
PCI Bus
IXP2400
Quad OC-12 PHY
Oahu Quad Gig Phy
Phy Interface
Utopia 3 (2 X 8)
SPI-3 (2 X 8)
Amazon IXF6048 Quad OC12 POS/ATM Framer
Vallejo 4 x 1G Ethernet MAC
No Connect/No Use
62
IXP2400 Edge / Access Networks - Multiple Line
Card Solutions
CSIX Switch Fabric (3rd Party)
80 Gig to 1 TerabitSwitch Fabric
IXP2400
IXF6048
Txcvr
OC-48WAN Backbone
IXP2400
Slot n
63
IXP2800 10Gbps SONET line card
D R A M
D R A M
D R A M
RDRPacket Memory
Control Plane Processor
QDR SRAM Queues Tables
Q D R
Q D R
Q DR
Q DR
PCI 64/66
IXP2800 Ingress Processor
Fabric Interface Chip (FIC)
Calypso
CDR, DEMUX
15Gbs
10GbE OC-192c
10Gbs
SPI I/F
Fabric
CSIX I/F
Flow Ctl
CDR, DEMUX
15Gbs
10Gbs
IXP2800 Egress Processor
10 GbE WAN / PPP/ ATM/ OTN / SONET/ SDH
RDR Packet Memory
D R A M
D R A M
D R A M
Q DR
Q DR
Q DR
QDR SRAM Queues Tables
Q DR
64
IXP2800 10Port 1Gbps Ethernet line card
D R A M
D R A M
D R A M
RDRPacket Memory
Control Plane Processor
QDR SRAM Queues Tables
Q D R
Q D R
Q DR
Q DR
PCI 64/66
IXP2800 Ingress Processor
Fabric Interface Chip (FIC)
Ben Nevis
15Gbs
10x1GbE
10Gbs
SPI I/F
Fabric
CSIX I/F
Flow Ctl
15Gbs
10Gbs
IXP2800 Egress Processor
10 x 1 GbE LAN
RDR Packet Memory
D R A M
D R A M
D R A M
Q DR
Q DR
Q DR
QDR SRAM Queues Tables
Q DR
65
IXP2800 10Gbs Ethernet to SONET card
D R A M
D R A M
D R A M
RDRPacket Memory
Control Plane Processor
QDR SRAM Queues Tables
Q D R
Q D R
Q DR
Q DR
PCI 64/66
IXP2800 Ingress Processor
Ben Nevis
Calypso
Serveror DiskFarms
Metro Or WAN
10GbE 10x1Gb
10Gbs
10Gbs
SPI I/F
OC-1924xOC48
SPI I/F
Flow Ctl
10Gbs
10Gbs
IXP2800 Egress Processor
QDR SRAM Queues Tables
D R A M
D R A M
D R A M
Q DR
Q DR
Q DR
Q DR
RDR Packet Memory
66
IXP2800 system w/ SPI gasket
D R A M
D R A M
D R A M
Control Plane Processor
RDRPacket Memory
QDR SRAM Queues Tables
Q D R
Q D R
Q DR
Q DR
PCI 64/66
IXP2800 Ingress Processor
10Gbs
10Gbs
Dual Utopia3 or CSIX
Dual Utopia3 or CSIX

SPI4 2U3
x
SPI 2U3
SPI4 2U3
x
SPI gasket
67
IXP2800 system w/ chaining

• Glueless interface between IXP2800 devices

Control Plane Processor
PCI 64/66
IXP2800 Processor
IXP2800 Processor
IXP2800 Processor
10Gbs SPI-4
10Gbs SPI-4
10Gbs SPI-4
10Gbs SPI-4
D R A M
D R A M
D R A M
Q DR
Q DR
Q DR
Q DR
D R A M
D R A M
D R A M
Q DR
Q DR
Q DR
Q DR
D R A M
D R A M
D R A M
Q DR
Q DR
Q DR
Q DR
QDR SRAM Queues Tables
QDR SRAM Queues Tables
QDR SRAM Queues Tables
RDRPacket Memory
RDRPacket Memory
RDRPacket Memory
68
Agenda

• Overview
• What is a Network Processor?
• Overview of the IXP1200 Family
• Introduction to "IXP2400"
• Introduction to "IXP2800"
• Development Tools
• Example Intel IXA Applications
• Summary

69
IXP Family Feature Summary
70
Summary

• Intel IXA is not a point product it is a
  family of silicon and software with a supporting
  ecosystem
• The depth and breadth of Intel IXA is unmatched
  in the industry and this applies to silicon,
  software, tools, and the ecosystem
• Intel IXA addresses real applications with
  highly configurable solutions

Thank You