Idongesit Ebong 11 Jenna Fu 12 Bowei Gai 13 Syed Hussain 14 Jonathan Lee 15 Design Manager: Myron Kw

1
Idongesit Ebong (1-1)Jenna Fu (1-2)Bowei Gai
(1-3)Syed Hussain (1-4)Jonathan Lee
(1-5)Design Manager Myron Kwai
Presentation 11 Smart Cart 525
Stage XI 4 April 2005 LVS and Simulation

• Overall Project Objective
• Design a chip as part of a system that
  accommodates the growing demand for radio
  frequency identification (RFID) technology while
  creating a quicker, more convenient shopping
  experience.

2
Status

• Design Proposal
• Project chosen
• Verilog obtained/modified
• Architecture Proposal
• Behavioral Verilog simulated
• Size estimates/floorplanning
• Gate-level implementation simulated in Verilog
• Floorplan and more accurate transistor count
• Schematic Design
• Component Layout
• Functional Block Layout
• DRC of functional blocks
• LVS of functional blocks
• Chip Level Layout
• Full chip LVS
• Simulations (80)
• Schematic with loaded inputs/outputs
• ExtractedRC

3
Design Decisions

• Added buffers
• Resized buffers and extra buffering stage in SRAM
  made a significant difference in rise/fall times
• Slight modifications made to certain blocks to
  eliminate white (or black) space
• Adder
• Multiplier

4
Strategy for Testing

• Testing Strategy
• Test top (SRAM-adder-multiplier-logic-registers)
  separately from encryption, verify that outputs
  from registers to encryption inputs have good
  signal strength
• Test encryption block (done)
• Critical path estimation
• Registers-logic-multiplier-logic-registers

5
Previously (323.955 x 296.1)
6
Currently (324.765 x 289.89)
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Design Specifications
8
Simulations Encryption (ExtractedRC)
Rise Time 126.380 ps Fall Time 548.074 ps We
are aware of the difference in rise and fall
time working on it
9
Simulations Arithmetic Blocks

• Update on Adder
• ExtractedRC
• Rise Time 45.2762 ps
• Fall Time 47.411 ps
• Propagation Time 345.36 ps

10
Simulations SRAM

• Previously
• Schematic
• Rise Time 192.883 psFall Time 103.013
  psProp. Time 1.112 ns
• ExtractedRC
• Rise Time 275.000 psFall Time 147.000
  psProp. Time 947.000 ps

• Currently
• Schematic
• Rise Time 94.4536 psFall Time 74.6471
  psProp. Time 1.15343 ns
• ExtractedRC
• Rise Time 47.9381 psFall Time 40.7938
  psProp. Time 1.2883 ns

11
Problems Questions

• Buffers may still be added/modified in the
  multiplier this should not change much
  layout-wise
• Adder is weird
• Having to go through so many transmission gates
  may be a problem
• Update vdd! and gnd! werent connected, so
  nevermind D