Idongesit Ebong 11 Jenna Fu 12 Bowei Gai 13 Syed Hussain 14 Jonathan Lee 15 Design Manager: Myron Kw

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Idongesit Ebong (1-1)Jenna Fu (1-2)Bowei Gai
(1-3)Syed Hussain (1-4)Jonathan Lee
(1-5)Design Manager Myron Kwai
Presentation 6 Smart Cart 525
Stage VI 23 Feb. 2005 Component Layout and
Floorplan

• Overall Project Objective
• Design a chip as part of a system that
  accommodates the growing demand for radio
  frequency identification (RFID) technology while
  creating a quicker, more convenient shopping
  experience.

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Status

• Design Proposal
• Project chosen
• Verilog obtained/modified
• Architecture Proposal
• Behavioral Verilog simulated
• Size estimates/floorplanning
• Gate-level implementation simulated in Verilog
• Floorplan and more accurate transistor count
• Schematic Design
• Component Layout (25)
• Simulations

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Updated Floorplan Entire Design
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Layout Multiplier
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Layout Register
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Layout Carry-Select Adder
NETLISTS MATCH!!!
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Problems Questions

• Registers
• Which type to use? Current vs. NAND
  implementation of master-slave DFF
• Current HUGEbigger than our FA, might be even
  huger to make room for enable, reset, and clk
  signal wiring
• NAND smaller, but need to AND clk with enable
  signal in order to perform the function we want
  and not sure about messing with clk