EEL 3705 / 3705L Digital Logic Design

1
EEL 3705 / 3705LDigital Logic Design

• Fall 2006Instructor Dr. Michael FrankModule
  8 Introduction to Sequential Logic(Thanks to
  Dr. Perry for the slides)

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Wednesday, October 25, 2006

• Administrivia
• This weeks lab
• Midterm practical exams
• Homework assignment 4
• Due tonight
• Midterm Exam 2
• Nov. 6 (a week from Monday) Review on Nov. 1
• Plan for todays lecture
• Start coverage of sequential logic

3
Introduction to Sequential Design
4
Types of Logic Circuits

• Logic circuits can be
• Combinational Logic Circuits-outputs depend only
  on current inputs
• Sequential Logic Circuits-outputs depends not
  only on current inputs but also on the past
  sequence of inputs

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Sequential Circuit Models
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Combinational Logic Delay
Longest delay
Shortest delay
Longest timing delay 5ns5ns5ns5ns
20ns Shortest timing delay 5ns
We will use the longest delay to represent the
combinational logic (CL) delay, tcl
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Combinational Logic (CL) Cloud Model
Tcl20ns
Tcl20ns
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Memory
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Memory

• We will add memory (or registers) to our logic
  circuits. This will allow us to design
  sequential circuits.

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Registers

• We will represent registers with the following
  block diagram

Clock and reset are control signals Ns and ps are
data signals
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Sequential Systems

• Block Diagrams

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Sequential Systems General Block Diagram
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
CL Combinational Logic Cloud
Reg D Registers
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Sequential SystemsGeneral Block Diagram
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
X is the input data vector Y is the output data
vector
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Sequential SystemsBlock Diagram
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
Ns is the next state data vector Ps is the
present state data vector
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Sequential SystemsBlock Diagram
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
Notice we have a feedback path which combines the
ps data vector with the input vector to generate
a new ns data vector.
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Sequential SystemsBlock Diagram
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
Mathematically, we say
Or, ns is a function F of X and ps and Y is a
function H of ps.
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Example
F Logic
Register
Circuit Schematic
ns
ps
X input
H Logic (buffer)
Block Diagram
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Example
F Logic
Register
Circuit Schematic
ns
ps
X input
H Logic (buffer)
State Equations
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Finite State Machine (FSM)

• General Models

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Moore FSM General Block Diagram
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
CL Combinational Logic Cloud
Reg D Registers
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Moore FSM State Equations
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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Mealy FSM Block Diagram and State Equations
Next State
Present State
Input Vector
Output Vector
Feedback Path
Output Y is also a function of input X
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Mealy-Moore FSM Block Diagram and State Equations
Present State
Next State
Input Vector
Mealy Outputs
Moore Outputs
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State Diagrams
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State Bubble
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State Bubble Example
Conditional Transition
Unconditional Transition
State name S0 State value 00 Y 0 for this
state
We leave this state if upn1, We remain in this
state if upn0
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Memory Devices
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Memory Devices

• Data Latch (D-latch)
• Flip-flops (edge triggered)
• D-FF, D Register
• JK-FF
• T-FF

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D-FF Positive Edge TriggeredBlock Diagram
Symbol
4 inputs D,Clk,Pre,Rst One output Q
D Data Input Clk Clock Input Pre Preset
Input Rst Reset Input
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D-FF Truth Table
Symbol
Truth Table
D Clk
d d 1 0 0
d d 0 1 1
d 0 1 1
d 1 1 1
0 1 1 0
1 1 1 1
Equation (rising clock)
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D-FF Truth Table
Symbol
Truth Table
D Clk
d d 1 0 0
d d 0 1 1
d 0 1 1
d 1 1 1
0 1 1 0
1 1 1 1
Equation (rising clock)
Pre Preset Input (active low) Rst Reset Input
(active low) Highest priority
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D-FF Truth Table
Symbol
Truth Table
D Clk
d d 1 0 0
d d 0 1 1
d 0 1 1
d 1 1 1
0 1 1 0
1 1 1 1
Equation (rising clock)
D Data Input Clk Clock input Qn Register
Output
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FSM Examples
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Example 2-bit Up Counter

• State Diagram

Clock is implied
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Example 2-bit Up Counter

• State Table

State Value Assignment
S0 00
S1 01
S2 10
S3 11
Let
ps ns y
S0 S1 0
S1 S2 1
S2 S3 2
S3 S0 3
Output Vector
Let S0 reset state
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Example 2-bit Up Counter

• Truth Table

ps1 ps0 ns1 ns0 y1 y0
0 0 0 1 0 0
0 1 1 0 0 1
1 0 1 1 1 0
1 1 0 0 1 1
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Example 2-bit Up Counter

• Excitation Equations

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Moore FSM
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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Logic Diagram
No X Vector in this Example No H Logic needed
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Logic Diagram
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Flash Animation
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Example 3 2-bit Down Counter

• State Diagram

Clock is implied
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Example 2-bit Down Counter

• State Table

S0 00
S1 01
S2 10
S3 11
Let
ps ns y
S0 S3 0
S3 S2 3
S2 S1 2
S1 S0 1
Let S0 reset state
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Example 2-bit Down Counter

• Truth Table

ps1 ps0 ns1 ns0 y1 y0
0 0 1 1 0 0
0 1 0 0 0 1
1 0 0 1 1 0
1 1 1 0 1 1
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Example 2-bit Down Counter

• Excitation Equations

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Recall Moore FSM
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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Logic Diagram
Reg Block
F Logic
Y Vector
H Logic
No X Vector in this Example
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Logic Diagram
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Example 4 2-bit Up/Down Counter

• State Diagram

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Example 2-bit Up/Down Counter

• State Diagram

Shorthand Notation
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Example 2-bit Up/Down Counter

• State Table

ps ns upn ns upn y
S0 S1 S3 0
S1 S2 S0 1
S2 S3 S1 2
S3 S0 S2 3
S0 00
S1 01
S2 10
S3 11
Let
Let S0 reset state
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Example 2-bit Up/Down Counter

• Truth Table

upn ps1 ps0 ns1 ns0 y1 y0
0 0 0 0 1 0 0
0 0 1 1 0 0 1
0 1 0 1 1 1 0
0 1 1 0 0 1 1
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 1 0 0 1 1 0
1 1 1 1 0 1 1
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Example 2-bit Up/Down Counter

• Excitation Equations

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Recall Moore FSM
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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Logic Diagram
Reg Block
X Vector
F Logic
Y Vector
H Logic
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Logic Diagram
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Example 5 3-bit Arbitrary Counter

• Design a 3-bit arbitrary counter that will count
  in the following sequence
• 3,2,3,1,2,3
• If a state is not used reset it to state zero.
• How may states do we have?
• How many registers do we need?
• How many bits do we need for Y?

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Example 5 3-bit Arbitrary Counter

• State Diagram

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Example Arbitrary 3-bit Counter

• State Table

Assign State Values
Let
S0 000
S1 001
S2 010
S3 011 S4 100 S5 101 S6 110 S7 111
ps ns y
S0 S1 3
S1 S2 2
S2 S3 3
S3 S4 1
S4 S0 2
S5 S0 0
S6 S0 0
S7 S0 0
Let S0 reset state
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Develop Truth Table
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Example 2-bit Arbitrary Counter

• Develop Excitation Equations -- F Logic

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Develop Excitation Equations for Y
Y1
Y0
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Example 2-bit Arbitrary Counter

• Excitation Equations -- H Logic

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Recall Moore FSM
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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Logic Circuit
H
REG
F
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Logic Circuit
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Simulation
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Monday, October 30, 2006

• Administrivia
• This weeks lab
• Comparators and arithmetic
• Homework assignment 5
• Will be posted soon (if not already)
• Midterm Exam 2
• Nov. 6 (a week from today) Review this Thursday
• Plan for todays lecture
• Continue coverage of sequential logic

69
Wednesday, November 1, 2006

• Administrivia
• This weeks lab
• Comparators and arithmetic
• Homework assignment 5
• Will be posted soon (if not already)
• Midterm exam 2
• Postponing to Nov. 13th review next Wednesday
• Plan for todays lecture
• Continue coverage of sequential logic

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Example 5 2-bit Up/Down Counter with Active Low
Enable and Synchronous RESET (SRESET)

• State Diagram

Clock is implied
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Example 2-bit Up/Down Counter with Enable and
SRESET

• Functional Table

srn en upn Function
0 d d Synchronous Reset (sreset)
1 1 d Hold
1 0 0 Count Up
1 0 1 Count Down
Highest Level of Priority
Lowest Level of Priority
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State Table
Srn En upn ns
0 d d S0
1 1 d ps
1 0 0 ps1
1 0 1 ps -1
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Truth Table (5 variables!!)
Although, we could design this circuit directly
from the truth table we will use design
partitioning.
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Moore FSM Architecture
Next State
Present State
Output Vector
Input Vector
Feedback Path
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Partitioned Design
We have
srn
Srn En ns
0 d S0
1 1 PS
1 0 Count
en
Note, with the partitioned design we can reuse
already designed submodules to create the new
design.
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Top Level Block Diagram
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UP/Down Logic
Logic Circuit
Symbol
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Register Block
Symbol
Logic Circuit
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2 Bit 4x1 Mux
Circuit
Symbol
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1-bit 4x1 Mux
Logic Circuit
Symbol
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1-bit 2x1 Mux
Logic Circuit
Symbol
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Top Level Block Diagram
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Simulation
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Example 6 FSM Controller
State Diagram
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Truth Table for NS
Truth Table
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Kmaps for NS1 and NS0
NS1
NS0
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Truth Table and Equations for Y
Truth Table
Recall, Moore FSM, so Y will Not be a function of
T
By Inspection
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Logic Circuit
H
REG
F
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Simulation
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Memory Devices
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Flip-Flops
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D-FF Truth TableQn follows D on Rising Edge of
CLK
Symbol
Truth Table
D Clk
d d 1 0 0
d d 0 1 1
d 0 1 1
d 1 1 1
0 1 1 0
1 1 1 1
Equation (rising clock)
D Data Input Clk Clock input Qn Register
Output
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T-FF (Toggle)Changes state on every tick of CLK
Symbol
T Clk
D d 1 0 0
D d 0 1 1
d 0 1 1
d 1 1 1
0 1 1
1 1 1
Equation (rising clock)
Truth Table
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SR-FFSet gtQn1ResetgtQn0
Symbol
S R Clk
d d d 1 0 0
d d d 0 1 1
d d 0 1 1
d d 1 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1 ???
Equation (rising clock)
Truth Table
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JK-FF
Symbol
J K Clk
d d d 1 0 0
d d d 0 1 1
d d 0 1 1
d d 1 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1
Equation (rising clock)
Truth Table
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Example Design a JK-FF usingonly Logic and a
D-FF
Symbol
J K Clk
d d d 1 0 0
d d d 0 1 1
d d 0 1 1
d d 1 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1
Truth Table
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Example
State Table
State Diagram
Let s00 and s11
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JK-FF
Truth Table
Logic Equations
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Recall Moore FSM State Equations
Next State
Present State
Output Vector
Input Vector
Clock
Feedback Path
Reset
State Equations
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JK Example
F Logic
D-Register
Circuit Schematic
ns
ps
X input
H Logic (buffer)
Block Diagram
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JK Example
Circuit Schematic
Simulation
102
Latches
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D-Latch Block Diagram
Symbol
4 inputs D,E,Pre,Rst One output Q
D Data Input E Enable Input Pre Preset
Input Rst Reset Input
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D-Latch Truth Table
Symbol
Truth Table
D E
d d 1 0 0
d d 0 1 1
d 0 1 1
0 1 1 1 0
1 1 1 1 1
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D-LatchState Equations
Symbol
Truth Table
D E
d d 1 0 0
d d 0 1 1
d 0 1 1
0 1 1 1 0
1 1 1 1 1
Equation (level clock)
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SR-LatchState Equations
Symbol
Truth Table
S R
d d 1 0 0
d d 0 1 1
0 0 1 1
0 1 1 1 0
1 0 1 1 1
1 1 1 1 ???
Equation (level clock)
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Example
T-FF
D-FF
D-Latch
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Simulation
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Modular Sequential Logic
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Shift Registers

• Logic Design which manipulates the bit position
  of binary data by shifting it to the left or
  right.
• Major application
• Serial Data to Parallel Data converters

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Example

• Design a three-bit shift register with the
  following functions

S1 S0 Function
0 0 Synchronous Reset (sreset)
0 1 Shift Right
1 0 Shift Left
1 1 No Shift
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Partitioned Design
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No Shift Equations and Circuit
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Shift Left Equations and Circuit
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Shift Right Equations and Circuit
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Synchronous Reset Module
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Registers
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Total Design