Automatic Wrapper Generation of Custom IPs for Platform FPGAs Under the guidance of Prof' M'Balakris

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Automatic Wrapper Generation of Custom IPs for
Platform FPGAsUnder the guidance ofProf.
M.BalakrishnanDr. Kolin PaulPresented by
Tej Paul VermaM.Tech 2nd YearComputer
Applications
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What is a Custom IP?

• Custom IP
• User specified H/W module.

Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
FPU IP
Leon Architecture
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What is a wrapper ?

• Wrapper
• Module Enclosing custom IP to provide
  necessary interface to the design

Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
Wrapper Logic
AMBA BUS
Wrapper
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Motivation

• Platform dependent design tools
• Need for a Generic Embedded Development Kit.
• Automatic Wrapper Generation
• - a Module of the GEDK
• Leon based tool lacks this feature

Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
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Objective

• Design of a wizard for Automatic generation of
  wrappers of Custom IPs for the Leon Architecture.
  
• Embedding the wizard with the present
  configuration tool available for the Leon flow.

Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
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Project Overview
Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
( HDL Files )
Driver Files
Information About IP
Literature survey
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Initial Phase

• Porting Leon architecture on XUP board -- Mapping
  UCF files.
• GR-PCI-XC2V3000
  XUP- XC2PV30
• Manually Interfacing of Custom IPs

Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
NET "clk" LOC "AC13 -system
clock NET "txd1" LOC "F10" NET "rxd1" LOC
"C10" NET "txd2" LOC "F9" NET "rxd2" LOC
"E9"
Net sys_clk_pin LOCAJ15 Net sys_rst_pin
LOCAH5 Net fpga_0_RS232_Uart_1_ RX_pin
LOCAJ8 Net fpga_0_RS232_Uart_1_ TX_pin LOCAE7
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APB IPIF 1. Address Decoding. Address
Range Definitions for IPIF services
Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
Address Decode Implementation
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2. Register I/F
Provides read /write access to the user logic S/W
registers to perform transfer b/w IP and the Bus
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
Read/Write Restriction Array
Base0x0 Base0x4 Base0x8
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3. Software Reset Support
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References

• Performs a local reset of the User IP by
  writing a data key to a user assigned address.
• Resets the user Logic S/W registers as well as
  the IPIF registers.
• In addition to the Hardware Reset on the Board.

Hardware Reset
Reset to User Logic and other IPIF services
Reset Logic
Bus2IP_Data
S/W reset signal
0xA
Reset Register
myIP_Reset(baseaddr)
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4. Interrupt Control support
Interrupt Control Mechanism of Leon Architecture
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
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APB IPIF Interrupt Controller Block Diagram
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
APB Bus
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APB IPIF Interrupt Controller Logic
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
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GUI Design
Present Configuration Tool
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
Modification Create Custom IP Wrapper Button
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GUI Design ..contd
Main wizard
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
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GUI Design ..contd
Documentation and Help
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
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GUI Design ..contd
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
S/W Reset Support
S/W Register Support
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GUI Design ..contd
Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
S/W Register Support
Read/write restrictions
No of Registers
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GUI Design ..contd
Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
User Logic Interrupt Support
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Wizard Output Files

• HDL files
• a) IP_Name.vhd -- Top level vhd file of the
  custom IP wrapper which has instantiations of
  apb_ipif and user_logic entities.
• b) User_logic.vhd template file in which the
  user can instantiate custom IP and map the ports
  of the custom IP with the IPIC signals.

Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
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User_Logic.vhd template
entity user_logic is generic ( --USER
generics added here -- Bus protocol
parameters, do not add to or delete C_DWIDTH
integer
32 C_NUM_CE integer
10 C_IP_INTR_NUM
integer 2 ) port (
--USER ports added here -- Bus protocol
ports, do not add to or delete Bus2IP_Clk
in std_logic Bus2IP_Reset
in std_logic
IP2Bus_IntrEvent out
std_logic_vector(0 to C_IP_INTR_NUM-1)
Bus2IP_Data in
std_logic_vector(0 to C_DWIDTH-1) Bus2IP_BE
in std_logic_vector(0 to
C_DWIDTH/8-1) Bus2IP_RdCE
in std_logic_vector(0 to C_NUM_CE-1)
Bus2IP_WrCE in
std_logic_vector(0 to C_NUM_CE-1) IP2Bus_Data
out std_logic_vector(0 to
C_DWIDTH-1) ) end entity user_logic architectur
e IMP of user_logic is begin ------- ltSELF
TEST CODEgtInstantiate the component of the Custom
IP ------ end IMP
Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
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Wizard Output Files contd
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
2) Driver Files a) IP_Name.h -- It
contains the declarations of the macros, address
offsets and the driver functions
prototypes.
define newip_USER_SLAVE_SPACE_OFFSET
(0x00000000) define newip_SLAVE_REG0_OFFSET
(newip_USER_SLAVE_SPACE_OFFSET
0x00000000) define newip_SLAVE_REG1_OFFSET
(newip_USER_SLAVE_SPACE_OFFSET
0x00000004) de
fine newip_IPIF_INTR_SPACE_OFFSET
(0x00000080) define newip_INTR_DIPR_OFFSET
(newip_IPIF_INTR_SPACE_OFFSET
0x00000004) define newip_INTR_DIER_OFFSET
(newip_IPIF_INTR_SPACE_OFFSET
0x00000008) de
fine newip_Reset(BaseAddress) Io_Out32((BaseAddre
ss)(newip_RST_OFFSET), IPIF_RESET)
void newip_EnableInterrupt(lo
ng baseaddr_p) void newip_Intr_DefaultHandler(lon
g baseaddr_p) void newip_SelfTest(long
baseaddr_p)
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Wizard Output Files contd
Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
b) IP_Name.c -- It contains the definitions of
the functions declared in the above header file.
c) IP_Name_Main.c -- It contains the
main() function in which the user can write the c
application code.
void newip_SelfTest(long baseaddr_p)
Write to user logic slave
register(s) and read back Reset
the device to get it back to its default
state Enable all possible
interrupts and clear interrupt status
registers
include "newip.c" main()
catch_interrupt(newip_Intr_DefaultHandler, 3)
enable_irq(3) newip_SelfTest(baseaddr)
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Automatic Instantiation of Custom IP
Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
Leon3mp.vhd -- Top Level VHD file of the
Design
.
.. -----------------------------------------
------------------------------------ --- APB
Bridge and various periherals --------------------
----------- --------------------------------------
---------------------------------------
newip_wrapper entity work.newip generic map(
pindex gt 8, paddr gt 6, pirq gt 1 ,pmask gt
16fff ) port map (rst gt rstn, clk gt clkm,
apbi gt apbi, apbo gt apbo(8)) apb0
apbctrl -- AHB/APB bridge generic map
(hindex gt 1, haddr gt CFG_APBADDR, nslaves gt
16) port map (rstn, clkm, ahbsi, ahbso(1),
apbi, apbo ) .

Example Using an IP
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Project Flow
Wrapper ? Motivation Objective Overview
Initial Phase APB IPIF GUI Design Output
Files Project Flow References
Study Leon Architecture
Design on board
Wrapper Creation For Some Custom IPs
Case Study Xilinx EDK Wrapper Generation
Wrapper generation templates
MTP-1
Midsem MTP-1
Embedding wizard Into GRLIB tool
GUI Design and Automation
Enhancing IPIF Services
Consistency checking
Midsem MTP-2
MTP-2
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References

• Generic EDK feasibility Report ,Kritikal
  solutions pvt. Ltd., Noida, May-2006
• www.kritikalsolutions.com
• Leon Processor, Grlib IP core Library , GRMON
  debugger
• www.gaisler.com
• Leon_sparc_at_groups.yahoo.com
• Xilinx ISE, EDK
• www.xilinx.com
• ModelSim Simulator
• www.model.com
• www.mentor.com
• Previous Projects_at_IITD
• http//embedded.cse.iitd.ernet.in
  

Wrapper ? Motivation Objective Overview Init
ial Phase APB IPIF GUI Design Output
Files Project Flow References
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• THANKS

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Data Types in APB IPIF

• Address Range Definitions(ARD)
• 2. ARD Data Width Array
• 3. ARD Chip Enable array

back
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APB IPIF Implementation Address Decoding

• Device Selection
• no of common high order bits 13
• used for the Device selection

ARD1_Base 000000000000000000000000000000
00 ARD1_High 000000000000000000111111111
11111 ARD2_Base 0000000000000110000
0000000000000 ARD2_High
00000000000001111111111111111111
ARD3_Base 00000000000000010000000000000000
ARD3_High 00000000000000011111111111111111
back
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APB IPIF Implementation Address Decoding
CS(i)

• 2. CS(Chip Select) Decoder
• no of bits compared with the APB_Addr to select
  the
• corresponding CS signal
• ARD1 (CS(1)) 5
• ARD2 (CS(2)) 2
• ARD3 (CS(3)) 3

ARD1_Base 000000000000000000000000000000
00 ARD1_High 000000000000000000111111111
11111 ARD2_Base 00000000000001100000
000000000000 ARD2_High
00000000000001111111111111111111
ARD3_Base 00000000000000010000000000000000
ARD3_High 00000000000000011111111111111111
back
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APB IPIF Implementation Address Decoding
CE
BE
CS

• 3. CE(Chip Enable) Decoder
• No of s/w addressable registers required 10
• No of bits required for selecting a register(CE)
  log2(10) 4
• Size of each register 32 bits/8 4 bytes
• No of bits required for BE(Byte Enables)
  log2(4) 2

ARD1_Base 000000000000000000000000000000
00 ARD1_High 000000000000000000111111111
11111
back
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Leon Architecture

• LEON3 processor
• - Soft core processor
• - Open Source code
• - Highly Configurable
• - 32-bit Risc processor
• -Harvard Architecture
• Technology independent library of IP cores

back
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AMBA AHB bus

• High performance
• Pipelined operation
• Multiple bus masters
• Burst transfers
• Split transactions

back
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AHB Bus (Basic Transfer)
Master Drives Address and control
Master gets response from slave
Slave samples and responses
back
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AMBA APB bus

• Low power
• Latched address
• and control
• Simple interface
• Suitable for
• many peripherals

back
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APB Bus (Timing Diagrams)
Write Transfer
Read Transfer
back
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Example - 32-bit FPU
back
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Example - 32-bit FPU
void fpu_interrupt_handler() intrvalue
myfpu_ReadReg(baseaddr, myfpu_INTR_ISR_OFFSET)
myfpu_WriteReg(baseaddr, myfpu_INTR_ISR_OFFSET,
intrvalue) output myfpu_ReadSlaveReg4(base
addr) // Read output and status status
myfpu_ReadSlaveReg5(baseaddr) main()
catch_interrupt(fpu_interrupt_handler,
12) enable_irq(12) myfpu_EnableInterrupt(basea
ddr) operand1 0x00023a00 operand2
0x00073100 myfpu_WriteSlaveReg0(baseaddr,
operand1) myfpu_WriteSlaveReg1(baseaddr,
operand2) myfpu_WriteSlaveReg2(baseaddr,
0x00000000) // Add them with even
rounding myfpu_WriteSlaveReg3(baseaddr,
0x80000000) // Start operation(oth bit
1) myfpu_WriteSlaveReg3(baseaddr, 0x00000000)
// Stop operation for(i0ilt100000i)
//wait for the interrupt handler to get executed
fully printf("\noutput after addition is
x",output) printf("\nstatus is
x",status)
back
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Example - 32-bit FPU
grlibgt run entered the interupt routine of
fpu(results available) first operand is
23a00 second operand is 73100 output after
addition is 96b00 status is 10000000 Program
exited normally.
back