Solutions for Real Chip Implementation Issues of NoC and Their Application to MemoryCentric Networks

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Solutions for Real Chip Implementation Issues of
NoC and Their Application to Memory-Centric
Networks-on-Chip

• Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin
  Lee and Hoi-Jun Yoo
• Dept. of EECS
• Korea Advanced Institute of Science and
  Technology (KAIST)

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Outline

• Introduction
• Circuit Techniques for efficient NoC
  Implementation
• Memory-Centric NoC
• Architecture
• NoC operation
• Performance Evaluation Implementation Results
• Conclusions

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Introduction

• Our direction of NoC implementation

Slim Spider - Hierarchical star
Memory Centric NoC (Hierarchical star Shared
memory)
IIS - Configurable
PROTONE - Star topology
Star
Mesh
80-Tile NoC, Intel
RAW, MIT
Baseband processor NoC, STMicro, et. al.
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Hierarchical Star Topology (1/2)

• NoC topologies in Real Chips

- Basic Topologies
Processing Node (IP)
Crossbar Switch
Star (Heterogeneous)
Mesh (Homogeneous)
- Hierarchical Topologies
... Other Derivatives
Global Star, Local Mesh
Global Star, Local Star
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Hierarchical Star Topology (2/2)

• Energy Area comparison

Energy / Packet
Interconnection Area
? Hierarchical star topology has high energy/area
efficiency
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Techniques for efficient NoC

• From the Circuit Designers Viewpoint
• Keep it SIMPLE and make the Chip WORK!
• Chip aware protocol HW Complexity
• On-chip serialization Small Area
• Synchronization Clock Complexity
• Low voltage swing link Low Power
• Crossbar switch partial activation Low Power

Fancy Network Concepts are not necessary
Chip implementation and its Performance is more
important than the network itself.

• ISOCC, S.J. Lee, et. al. 2005

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Packet Format and Protocol

• Aligned packet format reduces hardware complexity

• Efficient link utilization
• Increased control complexity
• Reduced operation speed

• Reduced control/hardware Complexity
• Increased operation speed
• Link utilization may inefficient

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On-chip Serialization (1/2)

• Concept and effects of On-chip Serialization

Reduced Link Width
Reduced X-bar Switch
? Proper level of On-chip Serialization improves
NoC performance
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On-chip Serialization (2/2)

• High speed SERDES (WAFT)

? WAFT SERDES removes set-up/hold time overhead
of F/F to achieve high speed operation
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Synchronization

• Source synchronous - matched delay synchronizer

Strobe delay Phit delay tPD tBUFA tCQ
tBUFB
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Low voltage signaling

• Scheme and transceiver circuits

? Improves power efficiency of global long wires
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Crossbar Partial Activation

• Crossbar partial activation reduces unneeded
  power dissipation

? Applying crossbar partial activation to a 16x16
switch fabric results in maximum 43 power saving
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Memory-Centric NoC
Hierarchical Star Topology NoC
Shared Memory Communication
Shared Memory
SW
PE
PE

SW
PE
PE

• Low overhead inter-
• processor communication
• Low Scalability

• Concurrent data transactions
• Message passing overhead

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Memory Centric NoC Architecture (1/2)

• Overall Architecture
• 10 RISC processors
• 8 dual port memories
• 4 Channel controllers
• Hierarchical-star topology packet switching
  network
• Mesochronous comm.

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Memory Centric NoC Architecture (2/2)

• Architectural features

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Memory Centric NoC Operation (1/2)

• Overview of the MC-NoC operation

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Memory Centric NoC Operation (2/2)

• Valid check logic manages data coherency

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Memory Centric NoC - Application

• Target application
• SIFT based object recognition

Overall flow of the SIFT computation
? MC-NoC facilitates data transactions occurred
in SIFT feature calculation
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Memory Centric NoC Advantages (1/3)

• Task mapping on conventional mesh NoC

Mapping w/o contention
Contended mapping
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Memory Centric NoC Advantages (2/3)

• Task mapping on the proposed MC-NoC

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Memory Centric NoC Advantages (3/3)

• Flexibility of task mapping

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Memory Centric NoC Performance Report

• Average latency power breakdown

Power Breakdown
Average Latency
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Implementation Results

• Chip photograph specification

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Conclusion

• Real Chip implementation issues
• Simple architecture and circuits
• Chip performance Network performance
• Memory Centric NoC
• Hybrid of Shared Memory and Star topology
• Low overhead communication
• Concurrent inter-processor communications
• MC-NoC for object recognition processor
• 0.18um CMOS process
• 7.7mm x 5mm, 1.4W at 1.8V and 81.6GOPS

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