A 1V RF frontend for both HIPERLAN2 and 802.11a

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A 1 V RF front-end for both HIPERLAN2 and 802.11a
T. Taris, JB. Begueret, H. Lapuyade, Y.
Deval IXL laboratory, University of Bordeaux 1,
33405 Talence, France
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OUTLINE

• HIPERLAN2 and 802.11a requirements
• Wireless mass market design constrains
• LNA
• MIXER
• RF Front-end
• Measurement results
• Conclusions

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HIPERLAN2 and 802.11a requirements
Mixer
LNA
VGA
PBF
PBF
LO
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Wireless mass market constrains
Wireless applications Mass market
CMOS VLSI analog design
Power aware systems
Low Power / Low Voltage
lt10 mW / 1V
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LNA
Ftot FLNA(Fmixer-1)/GLNA
Input matching
Low noise figure
Low power Low voltage
Maximum signal collected
Ftot FLNA(Fmixer-1)/GLNA
Gain
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LNA
Tuned Load
Good Linearity
Reduce Miller Effect
out
Lg
MLNA
RF
bias
Ls
Inductive Degeneration
50? input matching
Low Noise Figure
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Mixer
Principle efficiency
Mixing operation
Gain
Low power Low voltage
Voltage dynamic range trade-off
Mixing principle brought into play
Linearity
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Mixer
Low-pass filter behavior
High-pass filter behavior
VFI
VLO
VRF
bias
In saturation region
Assuming
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RF Front-End
Rconv
Cd2
Cd1
Mmix
MLNA
LNA
Mixer
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Measurement results
S11 -26 dB
Isolation LOgtRF -34 dB

• Inductive degeneration matching

• Due to closeness of RF and LO port

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Measurement results
Gain (dB)
10
9
8
7
6
5
4
3
2
1
Supply Voltage (V)
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Gain 10 dB _at_ 1 V
ICP1-9 dBm IIP30 dBm

• Good input matching
• Architecture well suited to low voltage

• Efficiency of resistor load
• Bypass filter behavior

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Measurement results
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Conclusions

• Fulfill successfully both HIPERLAN2 and 802.11a
  requirements
• Operating under 1V and consuming only 6 mA, it
  is well suited to low power/low voltage
  applications
• implemented in CMOS VLSI technologie its weak
  bulkiness (750µm?500µm ) dedicates it to System
  On a Chip (SOC) applications

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Perspectives

• Improve isolation between LO and RF port
• Architecture without inductance (matching
  trade-off)
• Enhance the conversion gain (linearity trade-off)