EE%20201A/EE298%20Modeling%20and%20Optimization%20for%20VLSI%20Layout

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EE 201A/EE298Modeling and Optimization for
VLSI Layout
Instructor Lei He Email LHE_at_ee.ucla.edu
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Outline

• Course logistics
• Overview
• What are covered in the course
• What are interesting trends for physical design

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Instructor Info

• Email LHE_at_ee.ucla.edu
• Phone [phone]
• Office Engineering IV 68-117
• Office hours Tu/Th 2-3pm or by appointment
• The best way to reach me
• Email with EE201 in subject line

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About this Course

• One of selective course for EEs ECS Major Field
  Students
• Question in M.S. comprehensive exam / PhD prelims
• Offered every other spring
• Will be under another course number (EE205B)
• Related courses
• Manis EE202A Embedded Computing Systems (Fall)
• Ingrids EE201A on Advanced VLSI (Spring)
• Bill M-Ss EE204A on Compilers (Winter)
• My EE205A Fundamental to CAD (Winter)
• Manis EE206A Wireless Systems (Spring)
• My EE205B (every other Spring)

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Course Prerequisites

• Official prerequisite
• EE116B VLSI System Design
• But mainly self-contained
• Knowledge to help you appreciate more
• CS180 Introduction to algorithms

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EE205A and EE205B

• EE205A Fundamental to CAD of embedded systems
• System level performance/power/thermal modeling
  and optimization
• Synthesis scheduling and allocation, logic
  optimization and technology mapping
• FPGA circuits and architectures and placement and
  routing for FPGA
• EE205B Modeling and Optimization for VLSI layout
• Advanced algorithms for physical design
• Fundamentals of combinatorial algorithm
• Detailed performance, signal integrity, power and
  thermal models
• Incorporating physical design into system design

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VLSI Design Cycle
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VLSI Design Cycle (cont.)
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Simplified Physical Design Cycle
Partition
Front-end physical design
Floorplanning
Placement
Routing
Back-end physical design
Extraction and Verification
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Course Outline and Schedule

• Front-end physical design (4.5 weeks)
• Partitioning, floorplanning and placement
• Power and thermal modeling
• Algorithms divided and conquer, simulated
  annealing, genetic algorithm
• Project proposal due by end of fifth week
• Back-end physical design (4.5 weeks)
• Interconnect extraction and modeling
• Interconnect synthesis
• Noise modeling and avoidance
• Clock and power supply design
• Algorithms dynamic programming, linear
  programming
• Project report due the last day of the quarter

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Related VLSI CAD Conferences

• ACM IEEE Design Automation Conference (DAC)
• http//www.dac.com (San Diego, Young student
  program)
• International Conference on Computer Aided
  Design(ICCAD)
• Design, Automation and Test in Europe (DATE)
• Asia and South Pacific Design Automation
  Conference (ASP-DAC)
• International symposium on physical design
  (ISPD)
• International symposium on low power electronics
  and design
• International symposium on field programmable
  gate array
• IEEE International Symposium on Circuits and
  Systems (ISCAS)

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Related VLSI CAD Journals

• IEEE Transactions on CAD of Circuits and systems
  (TCAD)
• ACM Trans. on Design Automation of Electronic
  Systems (TODAES)
• IEEE Transactions on Circuits and Systems (TCAS)
• IEEE Trans. on VLSI Systems (TVLSI)
• IEEE Trans. on Computer
• Integration
• Algorithmica
• SIAM journal of Discrete and Applied Mathematics

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Money Talk for VLSI CAD

• Synposys, Cadence, Magma, Mentor Graphics,
• Over hundreds companies have booths at DAC
• Two of them are among the ten biggest software
  companies in the world
• But they are smaller than the biggest spin-off of
  EDA
• EDA is regarded as A-graded bonds for Venture
  Capitalists
• One of few IT segments still recruits heavily
  and offers salary higher than Intel/IBM
• EDA system is regarded as one of the most
  complicated software systems mankind ever built

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References for this Course

• Selected papers from TCAD, TODAES, and major CAD
  conferences such as DAC, ICCAD and ISPD
• Naveed A. Sherwani, "Algorithms for VLSI Physical
  Design Automation", 3rd Edition, 1998.
• H. Cormen, et al Introduction to Algorithms
  MIT Electrical Engineering and Computer Science
  Series 1990.
• H. Bakoglu, Circuits, Interconnects, and
  Packaging for VLSI, Addison Wesley
• Cong et al., Performance Optimization of VLSI
  Interconnect Layout, Integration, the VLSI
  Journal 21 (1996) 1--94.

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Grading Policy

• Homework 15
• Midterm (7th week) 20
• Course presentation 15
• Term project 50
• A ? score gt 85 and programming project

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Course Presentation (15)

• 23 student a team
• Survey an area (topics and resources specified by
  me on a continual basis)
• Prepare slides and do a 30-35 minute presentation
  in the class
• slides prepared jointly
• either all students share the presentation or I
  will select the speaker randomly at the
  presentation time
• Prepare a web site that should contain a report
  based on your survey, a bibliography, and links
  to resources and of course your slides

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Term Project (50)

• One of the following two
• One-person survey and critic of selected topic
  (at most 35)
• Individual programming project for a team of 2
  to 3 persons
• Coupled system design and physical design
• Floorplanning with thermal constraints
• 3D modeling and physical design
• Or any topic agreed by instructor
• Up to 30 minute presentation during the finals
  week, like a conference talk
• Up to 12 page report in the style of a technical
  conference paper
• ACM style http//www.acm.org/sigs/pubs/proceed/tem
  plate.htm

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Who should take this course

• It is another course
• Discuss wide scope of knowledge
• But research (presentation project) on your own
  focus
• For students who are motivated to
• Learn SI, power/thermal for advanced designs
• Learn algorithm basics without taking CS280
• Understand CAD better
• Become a CAD professional

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Complexities of Physical Design
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Moores Law and NTRS

• Moores Law
• The min. transistor feature size decreases by
  0.7X every three years (Electronics Magazine,
  Vol. 38, April 1965)
• True in the past 30 years, and expected to hold
  for another 10-15 years
• National Technology Roadmap for Semiconductors
  (NTRS97)

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Productivity Gap
10,000,000
100,000,000
1,000,000
10,000,000
58/Yr. Complexity growth rate
100,000
1,000,000
Logic Transistors/Chip (K)
Transistor/Staff-Month
10,000
100,000
1,000
10,000
21/Yr. Productivity growth rate
x
x
100
1,000
x
x
x
x
x
x
10
100
1
10
1998
2003
Chip Capacity and Designer Productivity
Source NTRS97
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Design Challenges in Nanometer Technologies

• Interconnect-limited designs
• Interconnect performance limitation
• Interconnect modeling complexity
• Interconnect reliability
• Impact of new interconnect materials
• Small feature size
• Process variations
• Leakage (50 of total power)
• High degree of on-chip integration
• Complexity and productivity
• Limitation of current design abstraction and
  hierarchy
• System on a chip and system in package or 3D
  technology
• Power/thermal barrier

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Design Styles
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Full Custom Design Style
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Standard Cell Design Style
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Gate Array Design Style (or Structured ASIC)
VDD
Metal1
Metal2
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Field-Programmable Gate-Arrays (FPGAs)

• Programmable logic
• Programmable interconnects
• Programmable inputs/outputs

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FPGA Design Style
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Comparisons of Design Styles
style
uneven height cells are also used
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Comparisons of Design Styles
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Packaging Styles
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Printed Circuit Board Model
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MCM Model
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Wafer Scale Integration
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Comparisons of Packaging Styles

• Merit propagation speed (inches/psec.)
  interconnection density (inches/sq. in).
• Interconnect resistance was not considered

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Increasingly on the Same Chip or in the Same
Package (SoC and SiP)

• SC3001 DIRAC chip (Sirius Communications)

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History of VLSI Layout Tools
One of the new trends SoC and SiP for 3D
technology
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Summary

• Physical design is the most complicated step in
  the VLSI design cycle
• Physical design is further divided into
  clustering, partitioning, floorplanning,
  placement, global and detailed routing.
  Extraction and verification is an important
  aspect.
• There are four major design styles -- full
  custom, standard cell, gate array (structured
  ASIC), and FPGAs.
• There are three alternatives for packaging of
  chips -- PCB, MCM and WSI. But increasingly, we
  design for SoC and SiP and will use 3D technology
• Automation reduces cost, increases chip density,
  reduces time-to-market, and improves
  performance.
• CAD tools currently lag behind fabrication
  technology, which is hindering the progress of
  IC technology

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Homework (due April 14th)

• Read ITRS roadmap executive summary and write one
  page summary and critic on one aspect related to
  your research or field
• http//public.itrs.net/Files/2001ITRS/Home.htm
• Search literature or web related to SoC, SiP and
  3D technology, summarize five papers on a
  coherent topic (e.g., technology, design, or CAD)
  and speculate potential need of CAD research
• Following style of conference paper
• With course project proposal in mind
• Submit homework in PDF via email
• Check out course website for notes of future
  lectures
• http//eda.ee.ucla.edu/EE201A-04Spring