High Performance MOS Current Mode Logic Circuits

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High Performance MOS Current Mode Logic Circuits
Saied Hemati Ph.D. Candidate Ottawa-Carleton
Institute for Electrical Computer Engineering
(OCIECE) Carleton University Ottawa, Canada
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Outline

• Introduction
• CML versus VML
• Different types of CML
• - ECL
• - CSL
• - MCML
• - DyCML
• - Feedback MCML
• A 10-Gbps MUX/DeMUX
• Conclusion

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• Motivations for new logic styles
• Higher speed.
• Lower power consumption.
• Lower area consumption.
• Lower fabrication cost.
• Higher robustness (environment noise ,
  fabrication fluctuations, ).
• Low noise operation.
• Lower complexity (design, optimization,
  test,).

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• What is wrong with CMOS?
• 1- It is not suitable for high speed
  applications.
• Turn off time and turn on time limit the
  maximum speed.
• Power consumption increases by frequency.
• Each input at least is connected to two gates.
• P-type devices play a key role in CMOS.
• Voltage swing is too large.
• Rate of charging and discharging is not
  constant.
• 2- High dynamic power dissipation.
• Large swing voltage.
• Large supply voltage and threshold voltage.

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What is Wrong With CMOS?
What is Wrong With CMOS?
What is Wrong With CMOS?
What is Wrong With CMOS?
What is Wrong With CMOS?

• 3- CMOS produces lots of noise.
• Sharp switching currents.
• Voltage variation.
• 4- CMOS suffers from low robustness.
• Propagation delay varies with supply voltage.
• Propagation delay varies with threshold voltage
  (80).
• Noise can degrade the performance.
• 5- CMOS consumes too much area.
• Pull up network.
• 6- Low degree of freedom in optimization.

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Current Mode Logic

• 1- Transistors are always on (fully or
  partially).
• Higher speed
• Low threshold devices can be used.
• - Lower Vdd .
• - Lower power dissipation.
• - Static power dissipation.

R1
R2
out
out
Inputs
I
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Current Mode Logic

• 2- Swing voltage is small.
• Higher speed
• Lower dynamic power dissipation.
• Lower noise generation .
• Lower noise margin.
• 3- Gates are based on n-type differential pair.
• Immunity to common mode noise (supply bounce).
• Smaller input capacitance.
• Transistors should be identical.

R1
R2
out
out
Inputs
I
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Current Mode Logic

• 4- Gates draw a static amount of current from
  power supply.
• Reduces the amount of spiking of the supply
  and substrate voltages
  (lower noise).
• Rate of charging and discharging is constant.
• - Higher level of freedom.
• Static power consumption.

R1
R2
out
out
Inputs
I
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Current Mode Logic

• 5- P-type devices are never used as switch.
• Higher speed.
• Lower number of transistors.
• 6- Pull up resistors are expensive.
• 7- Suitable power down techniques
  should be found.
• 8- The matching of fall and rise delays is not
  easy.

R1
R2
out
out
Inputs
I
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Emitter Coupled Logic (ECL)
ECL is the fastest known logic family for silicon
integrated circuits. ECL gates consists of -
differential amplifier. - temperature and
voltage compensated bias network. - Emitter
follower output.
Vref-1.25V
VOH -0.85V VOL -1.75V
ECL NOR/ OR
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Emitter Coupled Logic (ECL)
Chip Technology in top500 supercomputers
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Current Steering Logic (CSL)
Vdd
Vref
Ibias
A simple current mode logic with shortened swing
voltage. VOH VT Veff VOL ? Veff
Vout
B
C
D
A
A 4-input CSL NOR
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MOS Current Mode Logic (MCML)
Inputs and outputs are differential. Buffer and
Inverter gates are the same. Nor/Or/And/Nand
gates are the same. Mux/Xor gates are similar.
RFP
out
out
A
A
RFN
Buffer/ Inverter
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MOS Current Mode Logic (MCML)
RFP
RFP
Out(out)
Out(out)
out
out
B
B
B
B(B)
B (B)
A(A)
A
A(A)
A
RFN
RFN
And/ Nand (Or/Nor)
Xor
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MOS Current Mode Logic (MCML)
70
MCML XOR3
CMOS XOR3
2.5
60
CMOS
50
MCML
2
Energy-delay (pJps)
40
Energy-Delay (pJps)
30
1.5
20
10
1
0
500
1000
1500
2000
2500
3000
0
200
400
600
800
1000
Delay (ps)
Delay (ps)
Energy-Delay vs. Delay for MCML and CMOS
Inverters
Energy-Delay vs. Delay for MCML and CMOS XOR3
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MOS Current Mode Logic (MCML)
RFP
out
out
Vdd- Vswing
Vdd
RFN
-

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Dynamic Current Mode Logic (DyCML)
Current source and load resistors have been
redesigned. This configuration is similar to
differential cascode voltage swing logic (DCVSL).
Vdd
Vdd
CLK
CLK
out
out
Inputs
MCML Circuit
CLK
CLK
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Feedback MOS Current Mode Logic
Threshold voltage fluctuation in short channel
devices degrade matching between transistors in
CML circuits. Vth fluctuation is due to
fluctuation in fabrication process -
gate-oxide thickness. - channel length. -
Random placement of the channel
dopants. . . Negative feedback can be used to
improve robustness.
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Feedback MOS Current Mode Logic
out
out
A
A
RFN
Buffer/ Inverter
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Feedback MOS Current Mode Logic
For a first order system, gain-bandwidth is
constant and feedback decreases gain and
consequently increases bandwidth. Sensitivity of
the circuit to transistor mismatch decreases too.
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Feedback MOS Current Mode Logic
D_Type flip-flop
out
out
A
A
CLK
CLK
RFN
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Feedback MOS Current Mode Logic
A 10 Gb/s12 DeMux
Master Slave Master
D Q D Q CLK CLK
D Q D Q CLK CLK
D Q D Q CLK CLK
D D
Q0 Q0
Slave Master
D Q D Q CLK CLK
D Q D Q CLK CLK
Q1 Q1
CLK
CLK
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Feedback MOS Current Mode Logic
Power-delay product for different approaches
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Conclusion

• Current mode logic is attractive because of
• - high speed.
• - Energy-delay product can be optimized by
  designer.
• - immunity against noise.
• - quiet logic family.
• - suitable for low voltage applications.
• Optimization of CML circuits is challenging and
  need more research.

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References

• N. S. Pickles, M. C. Lefebvre, ECL I/O buffers
  for BiCMOS integrated systems a tutorial
  overview, IEEE Trans. Education, vol. 40, No. 4,
  pp.229-241, Nov. 1997.
• H. Ng, D. Allost, CMOS current steering
  logic for low-voltage mixed-signal integrated
  circuits, IEEE Trans. VLSI Systems, Vol. 5, No.
  3, pp.301-308, Sept. 1997.
• J. Musicer, An Analysis of MOS Current Mode
  Logic for Low Power and High Performance Digital
  Logic, M.Sc. Thesis, University of California,
  Berkeley, 2000.
• M.W. Allam, M. I. Elmasry, Dynamic current
  mode logic (DyMCL) A new low-power high
  performance logic style, IEEE J. Solid State
  Circuits, Vol. 36, No. 3, pp. 550-558, March.
  2001.
• A. Tanabe, et al , 0.18u CMOS 10Gb/s
  Multiplexer/Demultiplexer ICs using current mode
  logic with tolerance to threshold voltage
  fluctuation, IEEE J. Solid State Circuits, Vol.
  36, No. 6, pp. 988-996, June. 2001.