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Coordinator Prof' A' K' Majumdar

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2. EDA Tools. S. No. Item received. Received. Installed. No. of persons using the tool ... EDA Tool. Synopsys. 2. Date and duration. 14th- 18th July 2008. 3. ... – PowerPoint PPT presentation

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Title: Coordinator Prof' A' K' Majumdar


1
Indian Institute of Technology,
Kharagpur Resource Center
  • Coordinator - Prof. A. K. Majumdar
  • Co-coordinator - Prof. Swapna Banerjee
  • SMDP-II Project Report
  • Sponsored by
  • Ministry of Communication Information
    Technology,
  • New Delhi

2
1. Hardware
3
2. EDA Tools
Mentor TimeIt, FormalPro, IC is not used
4
3. Books and Furniture Status
  • No. of books purchased under SMDP-I 65
  • No. of books purchased under SMDP-II 80
  • Furniture procured Steel Almirahs, Computer
    Tables, Chairs, Sofa-Set.

5
4. Website preparation
  • Website has been prepared.
  • Address of website http//www.smdp.iitkgp.
    ernet.in

6
5. IEP/Vendor Trainings Conducted During 2008-09
7
6. International Guest Faculty Workshop
7
8
7. Manpower Generation
9
BACK
10
BACK
11
8.Details of Project Staff Employed
12
9. India Chip Program
13
  • SIGNAL PROCESSING FOR MEMS BASED PRESSURE
    SENSOR FOR BIOMEDICAL APPLICATION
  • In the above scheme, we are targeting the
    measurement of fetal pressure. For the purpose,
    two modes of display have been kept. One is
    direct display of the voltage through an external
    ADC and the other is a LED based display to
    indicate the range of pressure.

BACK
14
India Chip Program contd…..
15
i) Papers Presented in National / International
Conference s in which SMDP-II Financial Support
have been used
10. Papers/Publications
All Papers are listed in our smdp-2 website

16
  • An 8-bit, 1.8V, 500MS/s CMOS DAC with a Novel
    Four Stage Current Steering Architecture,
    International Symposium on Circuits and Systems
    (ISCAS),Seattle, Washington, USA, May 2008,
    pp.149-152.
  • An Equivalence-Checking Method for Scheduling
    Verification in High-Level Synthesis IEEE
    Transactions on Computer-aided design of
    Integrated Circuits and Systems, vol. 27, no. 3,
    March 2008.
  • 3. Methodology for Thermal Aware Topologies and
    Partitioning with Better Lateral Spreading ICM
    2008 (The 20th International Conference on
    Microelectronics)

BACK
17
BACK
18
ii) Publications in Journals and Conference
Proceedings in which SMDP II Lab Resources have
been used
All Papers are listed in our smdp-2 website

19
2005 List of Journal Publications
  • "Design and Fabrication of CMOS compatible High
    precision Tunneling Accelerometer", By T. K.
    Bhattacharyya, Debasish Paul, IEEE Conference on
    Nan scale Devices and Systems Integration NDSI
    2005, Houston, USA, (2005)
  • "Design and fabrication of a Monolithic Constant
    Fraction Discriminator", By V. D. Srivastava, P.
    K. Mukhopadhyay, S. K. Kataria, Y. P. Prabhakara
    Rao, Rejeena Rani and S. Kal, IMAPS National
    Conference on Microelectronics VLSI, IIT
    Bombay, (2005)
  • "Design of Static and Dynamic Tran linear Circuit
    based on CMOS CCII Tran linear Loop", By Debasis
    Dutta and Swapna Banerjee, 12th IEEE
    International Conference on Electronics, Circuits
    and systems, Gammarth, Tunisia, (2005)
  • "Etching of High aspect ratio Structure in
    Silicon using SF6/O2 and CF4/O2 Plasma", By I.S.
    Bajpayee, S. Das, S. Kal and S. K. Lahiri,
    International Conference on MEMS Semiconductor
    Nanotechnology, IIT Kharagpur, (2005)
  • "Flip-flop chining architecture for power
    efficient scan during test application", By S.
    Gupta, T. Vaish and S. Chattopadhyay, Asian Test
    Symposium, Kolkata, (2005)
  • "Electronic Mach Zehnder interferometer based
    quantum computing system", By Angik Sarkar, T. K.
    Bhattacharyya and Ajay Patwardhan, MEMSNANO
    International Conference on MEMS and
    Semiconductor Nanotechnology, IIT Kharagpur
    (2005)
  • "Evolving cellular automata for low power testing
    of circuits", By M. Chawla, H. Agrawal and S.
    Chattopadhyay, 9th VLSI Design and Test
    Symposium, Bangalore, (2005)
  • "Genetic algorithm approach for system-on-chip
    wrapper/TAM co-optimization using Rectangular
    packing", By G. Das, K. Vidyasagar, S.
    Chattopadhyay and H. Bhoumik, Asia South Pacific
    International Conference on Embedded SoCs,
    Bangalore (2005)
  • "Integrated core and interconnect testing with
    test-time and scan power minimization", By G.
    Das, S. Chattopadhyay and H. Bhoumik, 9th VLSI
    Design and Test Symposium, Banglore, (2005)
  • "Gate leakage current in MISIS-FET", By Angik
    Sarkar, T. K. Bhattacharyya, International
    Conference on MEMS and Semiconductor
    Nanotechnology, IIT Kharagpur, (2005)
  • "VLSI Architecture for FDTD Algorithm and its
    FPGA Implementation", By C. Aditya, A.
    Bhattachargee and I. Chakrabarti, Thirteenth
    International Conference on Advanced Computing
    and Communications (ADCOM), Coimbatore, India,
    (2005)
  • "A programmable built-in self-test for embedded
    DRAMs", By S, Banerjee, D. R. Chowdhury, and 
    B.B. Bhattacharya, IEEE International Workshop on
    Memory Technology, Design, and Testing Taiwan,
    (2005)
  • "Computer Aided Built-In Self-Repair for Embedded
    DRAMs", By S. Banerjee, and D. R. Chowdhury,

20
2005 List of Journal Publications
  • "Fault Diagnosis of VLSI circuits with Cellular
    Automata based Pattern Classifier", By B K
    Sikdar, N Galnguly and P Pal Chaudhuri EEE Trans.
    On CAD 24, 1115-1131 (2005)
  • "Current conduction mechanism in TiO2 gate
    dielectrics", By S. Chakraborty, M. K. Bera, S.
    Bhattacharya, and C. K. Maity Microelectronic
    Engineering, vol- 81, pp. 188-193 (2005)
  •  
  • "Modified Virtually Scalling-Free Adaptive CORDIC
    Rotator Algorithm and Architecture", By S.
    Banerjee, Koushik Maharatna, Eckhard Grass, Milos
    Krstic and Alfonso Troya IEEE Transaction on
    Circuits and systems for Video technology Vol.
    15, pp. 1463-1474 (2005)
  •  ?Data Folded Architecture for Running 3D DWT for
    4-tap Daubechies Filter?, By B. Das and Swapna
    Banerjee, IEE Proc. Circuits Devices Syst., Vol.
    152, No. 1, Feb. 2005 pp. 17-24.
  •  ?Modified Virtually Scaling ? Free Adaptive
    CORDIC Rotator Algorithm and Architecture?, By K.
    Maharatna, E. Grass, M. Krstic, A. Troya and
    Swapna Banerjee, IEEE Trans. On Circuits and
    Systems for Video Technology, Vol. 15, No. 11,
    Nov. 2005, pp. 1463-1474.
  • ''A Systematic framework for Validation and
    Debugging of Pipelined Simulators'',  By P P
    Chakrabarti, Subrat Panda, Rajeev Kumar, A. Roy,
    ACM Transaction On Design Automation and Embedded
    Systems (TODAES), vol-10, pp. 462-492, 2005
  • ''The Open Family of Temporal Logics Annotating
    Temporal Operators with Input Constraints'', By
    Pallab Dasgupta, A. Banerjee, ACM Transaction On
    Design Automation and Embedded Systems (TODAES),
    vol-10, pp. 492-522, 2005  

21
2005 List of Conference Papers
  • "Computer-Aided Test Tool for System-on-Chip", By
    S. Banerjee, and D. R. Chowdhury, VLSI Design
    Automation and Test (VDAT) 2005, Bangalore,
    India, (2005)
  • "Scan flipflop ordering with delay and power
    minimization during testing", By C. Giri, B. N.
    Kumar and S. Chattopadhyay, INDICON, Chennai,
    (2005)
  • "On-Line Testing of Digital Circuits for n-Detect
    and Bridging Fault Models", By S. Biswas, P.
    Srikanth, S. Mukhopadhyay, A. Patra, D. Sarkar,
    IEEE Asian Test Symposium, Kolkata, INDIA, (2005)
  • "Use of On-Line Testing for design of Reliable
    VLSI Circuits", By Santosh Biswas, Jintendra
    Agarwal, Dipankar Sarkar, Siddhartha Mukhopadhyay
    and Amit Patra, International Conference on
    Reliabiliability and Safety Engineering, IIT
    Kharagpur, (2005)
  • "Logic Synthesis and Technology Mapping of
    MUX-based FPGAs for Performance and Low Power",
    By M. Marik, and A. Pal, TENCON 2005, Melbourne,
    Australia, (1905)
  • "Battery-aware Code Partitioning for a text to
    Speech System", By Anirban Lahiri, Anupam Basu,
    Monojit Choudhury and Srobona Mitra, Design
    Automation and Test in Europe Conference, Munich,
    Germany,(0) 
  • "Boundary Fair Round Robin A Fast Fair
    Scheduler", By Arnab Sarkar, P. P. Chakrabarti,
    Rajeev Kumar, VDAT 2005, Bangalore, India(2005) 
  • "CryptoScan A secured Scan Chain Architecture,"
    By D. Mukhopadhyay, S. Banerjee, D RoyChowdhury
    and B. Bhattacharya, Asian Test Symposium 2005,
    Kolkata, India (2005) 
  • "Bounded model checking for Open-LTL", By
    Suchismita Roy, P. Dasgupta, P. P. Chakrabarti,
    VDAT 2005, Bangalore, India,(2005) 
  • "Interactive test-Bench Synthesis for
    Assertion-Based verification", By S. Banerjee, S.
    Chakravorty, B. Pal, P. Dasgupta, INDICON, India,
    (2005) 
  • "Performing Scan based Attack On a Stream Cipher
    hardware", By D. Mukhopadhyay, S. Banerjee and D.
    RoyChowdhury, National Workshop on cryptology,
    Shimoga, karnataka, India,(2005) 
  • "Programmable Galois Multiplier Using Cellular
    Automaton", By D. Mukhopadhyay and D.
    RoyChowdhury, 9th VLSI Design Automation and Test
    Conference, bangalore(2005) 
  • "SAST An Interconnection aware high level
    synthesis tool", By C. Karfa, J. S. Reddy, C. R.
    mandal, D. Sarkar and S. Biswas, 9th VLSI Design
    and Test Symposium (VDAT 2005), Bangalore, Indai
    (2005) 
  • "SAT based solution for consistancy problems in
    Formal Property Specification for Open system",
    By S. Roy, S. Das, P. Basu, P. Dasgupta, P. P.
    Chakrabarti, International Symposium on Computer
    Aided Design, san Jose, California (2005)

22
2005 List of Conference Papers Contd…
  • "Secured Key Agreement uSing cellular Automata',
    By D. Mukhopadhyay and D. RoyChowdhury, national
    Workshop on Cryptology, Shimoga, karnataka,
    (2005) 
  • "Test Plan Coverage by Formal Property
    verification", By P. Basu, S. Das, A. Banerjee,
    P. Dasgupta, P.P. Chakrabarti, VLSI Design and
    Test, India (2005)
  • ''A BIST Approach to On-line Testing of System
    on Chip (SoCs) Theory and Application'', By Amit
    Patra, Santosh Biswas, S Mukhopadhyay, B Maity, 
    IINC 2005, IIT Mumbai, 2005
  • ''A Hybrid System Approach to Failure Diagnosis
    of Analog VLSI Circuits A Case Study of DC-DC
    Buck Converter'', By Amit Patra, Santosh Biswas,
    S Mukhopadhyay, Jitendra Agrawal, D Sarkar, Salil
    Mighe, VDAT 2005, 2005
  • ''A Hybrid Systems Approach to On-Line Testing of
    Analog VLSI Circuits A Case Study of DC-DC Buck
    Converters Part 2 A Case Study'', By Amit Patra,
    Santosh Biswas, Baidurya Chatterjee, NCCDS 2005,
    IIT Mumbai INDIA., 2005
  • ''A Hybrid Systems Approach to On-Line Testing of
    Analog VLSI Circuits A Case Study of DC-DC Buck
    ConvertersPart1 Theory'', By Amit Patra, Santosh
    Biswas, S Mukhopadhyay, D Sarkar, NCCDS 2005, IIT
    Mumbai INDIA., 2005
  • ''A Novel Method for On-Line Testing of Mixed
    Signal System On a Chip A Case study of Base
    Band Controller'', By Amit Patra, Santosh Biswas,
    S Mukhopadhyay, Baidurya Chatterjee, 29th
    National System Conference, IIT Mumbai, INDIA,
    2005
  • ''A Simple Wide-Band Compact Model and Parameter
    Extraction using Particle Swarm Optimization of
    On-Chip Spiral Inductors for Silicon RFICs'', By
    Sushanta Kumar Mandal, Arijit De, Amit Patra,
    Shamik Sural ,  ACM Great Lakes VLSI Symposium,
    2005
  • ''A Single circuit solution for Voltage
    Sensors'', By Pradip Mandal, S.S. Prasad,  IEEE
    International Symposium on Circuits and Systems
    (ISCAS), Kobe, 2005
  • ''A verification system for transient response of
    analog circuits using model checking'', By P P
    Chakrabarti, T. Rai Dastidar, VLSI, 2005
  • ''An Improved Control scheme for Multiphase Buck
    Converter Circuits used in Voltage Regulator
    Modules'', By Jitendra Agrawal, D. Kastha, B.
    Culpepper, International Conference on Power
    Electronics and Drives Systems, 2005. PEDS 2005.,
    2005
  • ''Bounded Model Checking for OpenLTL'', By P P
    Chakrabarti, Pallab Dasgupta, S. Roy, VDAT, 2005
  • ''Compact Wide-Band Modelling of Spiral Inductors
    for RFICs using Particle Swarm Optimization'', By
    Sushanta Kumar Mandal, Arijit De, General
    Assembly of International Union of Radio Science,
    New Delhi, India, 2005
  • ''Design and Implementation of RF Front End for
    Ultra Wide Band Systems'', By T K Bhattacharya, A
    S Dhar, N B Chakraborty, Ashudeb Dutta, Prabir
    Saha, Arindam Basu, Sourish Haldar, XXVIIIth
    General Assembly of International Union of Radio
    Science (URSI). New Delhi, 2005
  • ''Design Issues in Switched Capacitor Ladder
    Filters'', By A S Dhar, Arindam Basu, 18th
    International VLSI Design Conference, 2005
  • ''Design of Second-Order Sub-bandgap Mixed-Mode
    Voltage Reference Circuit for Low Voltage
    Applications'', By Rajarshi Paul, A.Patra, S.
    Baranwal, K.dash,  IEEE International VLSI Design
    Conference, 2005
  • ''Formal Methods for Analyzing the Completeness
    of an Assertion Suite against a High-Level Fault
    Model'', By P P Chakrabarti, Pallab Dasgupta,
    Chittaranjan Mandal, S. Das, A. Banerjee, P.
    Basu, L. Fix., VLSI, 2005
  • ''Fully Integrated CMOS Frequency Synthesizer for
    ZigBee Applications'', By T K Bhattacharya,
    Ashudeb Dutta,  Saurabh Kumar Singh, IEEE VLSI
    Design Conference, India, 2005
  • ''H-DBUG A High-level Debugging Framework for
    Protocol Verification using Assertions'', By P P
    Chakrabarti, Pallab Dasgupta, A. Nandi, B. Pal,
    N. Chhetan, INDICON, 2005

23
2005 List Of Conference Papers Contd…
  • ''IEEE 802.15.4/ZigBeeTM Compliant IF Limiter and
    Received Signal Strength Indicator for RF
    Transceiver'', By T K Bhattacharya, Ashudeb
    Dutta, Rajshekhar Vaijinath,  IWWAN workshop,
    London UK, 2005
  • ''Interactive Test-Bench Synthesis for
    Assertion-Based Verification'', By Pallab
    Dasgupta, A. Banerjee, S. Chacrovorty, B. Pal, 
    INDICON, 2005
  • ''Low Power LVDS Receiver for 1.3Gbps Physical
    Layer (Phy) Interface'', By Pradip Mandal, Gunjan
    Mandal, IEEE International Symposium on Circuits
    and Systems (ISCAS), Kobe, 2005
  • ''Reduction in Spectral Peaks of DC-DC Converters
    using Chaos-Modulated Clock'', By Rupam
    Mukherjee, Shuvabrata Nandi, Soumitro Banerjee,
    IEEE International Symposium on Circuits and
    Systems (ISCAS), 2005
  • ''Reduction of Electromagnetic Interference of
    DC-DC Converters using Chaotically Modulated
    Clock'', By Rupam Mukherjee, Rajneesh Malav,
    Shuvabrata Nandi, Soumitro Banerjee, National
    Power Electronics Conference, 2005
  • ''SAST An Interconnection aware high level
    synthesis tool'', By Santosh Biswas, Chandan
    Karfa, Chittaranjan Mandal, Dipankar Sarkar, J.
    S. Reddy, 9th VLSI Design and Test (VDAT'05),
    2005
  • ''SAT based solutions for Consistency Problems in
    Formal Property Specifications for Open
    Systems'', By P P Chakrabarti, Pallab Dasgupta,
    S. Roy, S. Das, P. Basu,  ICCAD, 2005
  • ''Scoreboard Directed Dynamic Constraint
    Modification for Higher Simulation Coverage'', By
    P P Chakrabarti, Pallab Dasgupta, B. Pal, A.
    Nandi, S. Ray, A. Banerjee, SNUG, 2005
  • ''Syntactic Transformation of Assume-Guarantee
    Assertions From Sub-modules to Modules'', By P P
    Chakrabarti, Pallab Dasgupta, P. Basu, VLSI, 2005
  • ''Syntax-driven Approximate Coverage Analysis for
    an Assertion Suite against a High-Level Fault
    Model'', By P P Chakrabarti, Pallab Dasgupta, S.
    Das, P. Basu, VDAT, 2005
  • ''Test Plan Coverage by Formal Property
    Verification'', By P P Chakrabarti, Pallab
    Dasgupta, P. Basu, S. Das, A. Banerjee, VDAT,
    2005
  • ''Trimming Methodologies for compensating process
    variation errors in Second-Order Bandgap Voltage
    Reference Circuits'', By Rajarshi Paul, Faruk
    Nome, A. Patra, B. Culpepper, IAESTED
    International conference on circuits and systems,
    2005
  • ''Use of On-Line Testing for Design of Reliable
    VLSI Circuits'', By Amit Patra, Santosh Biswas, S
    Mukhopadhyay, Jitendra Agrawal, D Sarkar,
    International Conference on Reliability and
    Safety Engineering, IIT Kharagpur, 2005
  • ''Verilog-A Modeling of Parasitic and Biasing
    effects on PSRR Behavior of Brokaw Bandgap
    Voltage Reference'', By Rajarshi Paul, A. Patra,
    S. Mukhopadhyay, 9th VLSI Design and Test
    Symposium, Bangalore India, 2005
  • ''A BIST Approach to On-line Testing of System on
    Chip (SoCs)? Theory and Application'', By Amit
    Patra, Santosh Biswas, S  Mukhopadhyay, B Maity
    ,  IINC 2005, IIT Mumbai, 2005 
  • "A hierarchical cost tree mutation approach to
    optimization of analog circuits", By Somani, P.
    P. Chakrabarti, A. Patra, 18th International
    Conference on VLSI Design, Kolkata, India,
    3/1/2005, 535-538, IEEE Computer Science Press,
    2005 
  • "Mixing global and local competition in genetic
    optimization based design space exploration of
    analog circuits", By Somani, P. P. Chakrabarti,
    A. Patra, ACM/IEEE Design Automation and Test in
    Europe (DATE), Munich, Germany, 7/3/2005,
    1064-1069, ACM/IEEE, 2005. 
  • "Crosstalk aware Line Search Algorithm for Analog
    Routing", By Subhashis Mandal, Abhishek Somani,
    Jitendra Agarwal, Shamik Sural, Amit Patra, Ninth
    VLSI Design and Test Symposium, Bangalore, India,
    August, 2005 
  • "UML based Object Oriented Methodology for Analog
    Test Structure Design Automation", By Subhashis
    Mandal, Soumya Pandit, Abhishek Somani, Shamik
    Sural, Amit Patra, Ninth VLSI Design and Test
    Symposium , Bangalore, India, August, 2005

BACK
24
2006 List of Journal Publication
  • 'A Discrete Event System Approach to On-Line 
    Monitoring of Digital VLSI Circuits'', By Amit
    Patra, Santosh Biswas, S  Mukhopadhyay, D Sarkar
    ,  Journal of System Science and Engineering,
    India, 2006      
  • "A Formal Approach to On-Line Monitoring of 
    Digital VLSI Circuits Theory, Design and 
    Implementation'', By Amit Patra, Santosh Biswas,
    S  Mukhopadhyay , Journal of Electronic Testing
    Theory and Applications,vol-21, pp. 503-537, 
    2006 
  • "An Integrated DFT Solution for Mixed-Signal
    SOC", By S. Banerjee, D. Mukhopadhyay, C.V.
    GuruRao and D.Roy Chowdhury, IEEE Transactions
    on  Computer-Aided Design of Integrated Circuits
    and Systems, Volume 25,  Issue 7, Jul 2006,
    Page(s)1368 ? 1377 
  • "A New Approach to Analyze a Nanoscale CMOS
    Buffer", By Manisha Pattanaik and S. Banerjee
    WSEAS Transaction on Circuits and Systems Vol. 5,
    pp 190-195 (2006) 
  • "Analysis of interface states of
    Al/TiO2/SiO.3Ge0.7 MIS structure using
    conductance technique", By S. Chakraborty, M. K.
    Bera, P. K. Bose, and C. K. Maiti Semicond. Sci.
    Technol. vol-21, pp. 335-340, (2006) 
  • "An Integrated DFT Solution for Mixed-Signal
    SOC", By S. Banerjee, D. Mukhopadhyay, C.V.
    GuruRao, and D.Roy Chowdhury, IEEE Transactions
    on Computer-Aided Design of Integrated Circuits
    and Systems, Vol. 25,(7) pp 1368 (2006) 
  • "Bulk micromachining of silicon in TMAH-based
    Etchants for Aluminum Passivation and Smooth
    Surface", By K. Biswas, S. Das, D. K. Maurya, S.
    Kal and S. K. Lahiri Microelectronics Journal
    Vol. 37, pp.321-327 (2006) 
  • "Determination of the valence band offset and
    minority carrier lifetime in Ge-rich layers on
    relaxed SiGe", By S. Chakraborty, M. K. Bera, S.
    Bhattacharya, P. K. Bose, and C. K. Maity Thin
    Solid Films, vol- 504 pp. 73-76 (2006) 
  • "High Frequency Characterization and continuum
    modeling of ultrathin high-k (ZrO2) gate
    dielectrics on strained Si", By M. K. Bera, S.
    Chakraborty, S. Saha, D. Paramanik, S. Varma, S.
    Bhattacharya, and C. K. Maiti Thin Solid Films,
    vol-504, pp. 183-187 (2006) 
  • "Interface properties of room temperature grown
    oxide on Si0.15Ge0.85 layers", By R. Das, M. K.
    Bera, S. Chakraborty, A. R. Saha, and C. K. Maiti
    J. Electrochem. Soc. vol-153, pp. 511-514 (2006) 
  • "Rapid Thermal Oxidation of Ge-rich Si1-xGex
    Heterolayers", By M. K. Bera, S. Chakraborty, G.
    K. Dalapati, S. Chattopadhyay, S. K. Samanta, W.
    J. Yoo, A. K. Chakraborty, Y. Butenko, L. Siller,
    M. R. C. Hunt, S. Saha, and C. K. Maiti J. Vac.
    Sci. Technol.A, 24, 84-90 (2006) 
  • "An Integrated DFT Solution for Mixed-Signal
    SOC", By S. Banerjee, D. Mukhopadhyay, C.V.
    GuruRao, and D. Roy Chowdhury IEEE Transactions
    on Computer-Aided Design of integrated Circuits
    and Systems Vol. 25,(7) pp 1368- (2006)
  • "BDD-based synthesis of Logic Functions Using
    Adiabatic Multiplexers", By Gopal Paul, Sambhu N.
    Pradhan, Bhargab B. Bhattacharya, Ajit Pal and
    Annapurna Das International Journal on Systemic,
    Cybernetics, and Informatics vol. 1, pp. 44-49
    (2006)

25
2006 List of Journal Publication Contd…
  • "CMOS Compatible Bulk Micro machined Silicon
    Piezoresistive Accelerometer with Low Off-axis
    Sensitivity", By S. Kal, S. Das, D.K.Maurya,
    K.Biswas, A. Ravi Shankar and S. K. Lahiri,
    Microelectronics Journal, Vol 37, No.1, pp22-3
    (2006)
  • "Leakage Current Characteristics and Energy Band
    Diagram of AI/ZrO2/Si0.3Ge0.7 hetero-MIS
    structures", By S. Chakraborty, M. K. Bera, G. K.
    Dalapati, D. Paramanik, S. Varma, P. K. Bose, S.
    Bhattacharya, and C. K. Maiti Semicond. Sci.
    Technol. 21, 467-472 (2006)
  • "Power Delay Optimization of Nan scale CMSO
    Inverter Using Geometric Programming", By Manisha
    Pattanaik, Swapana Banerjee and Bikram K.
    Bahinipati WSEAS Transactions on Circuits and
    Systems Vol. 5pp. 536-541 (2006)
  • "CORDIC-based unified VLSI architecture for
    implementing window functions for real time
    spectral analysis", By K. C. Ray and A. S. Dhar
    IEE Proc. Circuits, Devices Syst., vol. 153, pp.
    539-544 (2006)
  •  ?A New Approach to Analyze a Nanoscale CMOS
    Buffer?, By Manisha Pattanaik and Swapna
    Banerjee,  WSEAS Transactions on Circuits and
    Systems, Issue 2, Vol. 5, February 2006.
  •  ?Power Delay Optimization of Nanoscale CMOS
    Inverter Using Geometric Programming?, By Manisha
    Pattanaik, Swapna Banerjee and Bikram K.
    Bahinipati,  WSEAS Transactions on Circuits and
    Systems, Issue 4, Vol. 5, April 2006.
  • ''A Discrete Event System Approach to On-Line
    Monitoring of Digital VLSI Circuits'', By Amit
    Patra, Santosh Biswas, S Mukhopadhyay, D
    Sarkar,Journal of System Science and Engineering,
    India (in-press)., 2006
  • ''CORDIC-based unified VLSI architecture for
    implementing window functions for real time
    spectral analysis'', By A S Dhar, Kailash Chandra
    Ray,IEE Circuits, Devices and Systems., vol-153,
    pp. 1922-1934, 2006
  • ''Design Intent Coverage - A new paradigm for
    Formal Property Verification'', By P P
    Chakrabarti, Pallab Dasgupta, P. Basu, S. Das, A.
    Banerjee, C.R. Mohan, L. Fix, R. Armoni , IEEE
    TCAD, vol-25, pp. 1922-1934, 2006
  • "Reasoning about Timing Behavior of Digital
    Circuits using Symbolic Event  Propagation and
    Temporal Logic", By Arijit Mondal, P. P.
    Chakrabarti, IEEE  Transactions on Computer Aided
    Design of Integrated Circuits amp Systems, 25 
    (9), pp 1793   (2006)  

26
2006 list of Conference Papers
  • "A Low Power 1.8 V 4-Bit 400-MHz Flash ADC in
    0.18u Digital CMOS", By Subhadeep,  Daibashish
    Gangopadhyay, T. K. Bhattacharyya, IEEE VLSI
    2006, Hyderabad, India, (2006)
  • "A Low Power 6-bit A/D Converter Achieving 10-bit
    Resolution for MEMS Sensor Interface using
    Time-interleaved Delta Modulation", By K. De, 
    Proc. 9th International Conference on VLSI Design
    (VLSI Design 2006), Hyderabad, India, 3-7
    January, 2006.
  • "Optimal Huffmnan coding for reducing power in
    System-On-Chip testing", By C. Giri, B. M. Rao
    and S. Chattopadhyay, CSI-EAIT, Kolkata, (2006)
  • "An Efficient FPGA Implementation of a Hash
    Algorithm Based on cellular Automata", By Roshni
    Chatterjee and D. Roy Chowdhury, Proceedings of
    VDAT 2006, Goa, India.
  • "Built-In Self-Test for Flash Memory Embedded in
    SOC", By S. Banerjee and D.Roy Chowdhury,
    Proceedings of 3rd  IEEE International Workshop
    on Electronic Design, Test and Applications,
    17-19 Jan. 2006, Malaysia, Page(s)379 - 384.
  • "An efficient scan tree design for compact test
    pattern set", By S. Banerjee, D.R. Chowdhury, and
    B.B. Bhattacharya, Proceedings of 19th
    International Conference on VLSI Design, 2006,
    3-7 Jan., 2006.
  • "Low-power BDD-based Logic Synthesis using
    Dual-rail  Static DCVSPG Logic", By Gopal Paul, 
    Sambhu N. Pradhan, Bhargab B. Bhattacharya.,
    IEEE Asia Pacific Conference on Circuit and
    System, December 2006, Singapore.
  • "An Approach to Architectural Enhancement for
    Embedded Speech Applications". By Dey S., Biswas
    S., Mukhopadhyay A., Basu A., Proceedings of the
    19th International Conference on VLSI Design
    2006, Hyderabad (pp. 371-376).
  • "Sanyog An Iconic Communication Aid for Children
    Suffering from Cerebral Palsy and Motor Neuron
    Disorders", By Mukhopadhyay A., Dey S., Saraswat
    P., Biswas S.,  Nori V. S., Bhattacharya S. ,
    Basu A., Proceedings of the 19th International
    Conference on VLSI Design 2006, Hyderabad
  • "Design and Implementation of a FPGA Based
    Portable Syatem for ECG Signal Acquisition,
    Processing and Monitoring", By Prashant Agrawal,
    Abhijeet Kumar,Indian Conference on Medical
    Informatics and Telemedicine, ICMIT 2006, IIT
    Kharagpur, India.
  • "Power Aware BDD-based Logic Synthesis Using
    Adiabatic Multiplexers", By Sambhu N. Pradhan,
    Gopal Paul, Bhargab B. Bhattacharya., IEEE ICECE-
    2006, Bangladesh.
  • "A Formal Approach for High Level Synthesis of
    Linear Analog Systems", By Soumya Pandit,
    Chittaranjan Mandal, Amit Patra , Proceedings of
    ACM/IEEE GLSVLSI 2006, Philadelphia, USA, pp
    345-348, April 30 - May 2, 2006.

27
2006 List of Conference Papers Contd…
  • "A Hybrid Search Procedure for System-Level
    Analog Design Space Exploration used in High
    Level Synthesis of Analog Systems", By Soumya
    Pandit, C R Mandal, Amit Patra , Proceedings of
    IEEE CODEC-06, Hyatt Regency, Saltlake, 18-20
    Dec, 2006.
  • "High-level Synthesis of Linear Analog Systems",
    By Soumya Pandit, Chittaranjan Mandal, Amit
    Patra, Proc. of International Conference on
    Emerging Applications of IT, Elsevier, Science
    City, Calcutta, pp 389-392, Feb 10-11, 2006.
  • "High Level Synthesis of Higher Order Continuous
    Time State Variable Filter with Minimum
    Sensitivity and Hardware Count", By Soumya
    Pandit, Chittaranjan Mandal, Amit Patra,
    Proceedings of DATE 06, ICM, Munich, Germany, pp
    1203-1204, Mar 6-10, 2006.
  • "Yield Aware Approach For Low Power Synthesis",
    By A. Jana.,IEEE ICECE- 2006, Bangladesh.
  • "High Speed Power Efficient CGIC Digital Filters
    for VLSI Applications", By Gopal Paul., IEEE
    INDICON, India. September 2006.
  • 'On Finding the Minimum Test Set of a BDD-based
    Circuit", By Gopal Paul, Bhargab B. Bhattacharya.
    ,ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI-
    2006), Proceeding pp. - 169-172, Philadelphia,
    USA.
  • "Sizing for Low Power" , International Conference
    on Computer Communication Engineering
    (ICCCE'06)", By A. Jana. , proceedings of the
    ICCCE'06 pp. - 1259-1264 Malyasia, May 2006.
  • ''A Cellular Automata Based Approach for
    Generation of Large Primitive Polynomial and its
    Application to RS-coded MPSK Modulation'', By
    Debdeep Mukhopadhyay, D. Bhattacarya, D.
    Mukhopadhyay, D. RoyChowdhury, International
    Conference on Cellular Automata for Research and
    Industry (ACRI 2006), 20-23 September 2006,
    Perpignan, France, 2006
  • ''A Debugging Utility for Assertion-based
    Protocol Verification'', By P P Chakrabarti,
    Pallab Dasgupta, B.Pal, A.Nandi,EAIT, 2006
  • ''A Formal Verification Method of Scheduling in
    High-level Synthesis'', By Chandan Karfa,
    Chittaranjan Mandal, Dipankar Sarkar, Chris
    Reade,In 7th IEEE International Symposium on
    Quality Electronic Design (ISQED06), 2006
  • ''A framework for estimating peak power in
    gate-level circuits'', By P P Chakrabarti, Pallab
    Dasgupta, D.Chakraborty, A. Mondal, International
    workshop on Power and Timing Modeling,
    Optimization and Simulation (PATMOS),
    Montpellier, France, 2006, 2006
  • ''A Novel Control technique For Single-Inductor
    Multiple-Output DC-DC buck Converters'', By Amit
    Patra, Souvik Chattopadhyay, Pradipta Patra, S.
    Samanta, D. Kastha, International Conference on
    Industrial Technology, 2006
  • ''A VHF OTA-C topology having low phase error
    with Gm tuning'', By Pradip Mandal, Kshitij
    Yadav, ICCCAS, China, 2006
  • ''An efficient methodology for automatic test
    pattern generation and testing of digital
    circuits in mixed signal systems'', By Amit
    Patra, Santosh Biswas, S Mukhopadhyay, M.
    Rajaneesh, A Roy, Second international conference
    on reliability Safety, IIT KHARAGPUR, 2006
  • ''Analysis and Characterization of On-Chip Spiral
    Inductors on Silicon using Electromagnetic
    Simulator'', By Sushanta Kumar Mandal, Ashudeb
    Dutta and Amit Patra,  3rd International
    Conference on Computers and Devices for
    Communication (CODEC-06), 2006

28
2006 List of Conference Papers Contd…
  • 'Analysis and Characterization of On-Chip Spiral
    Inductors using Electromagnetic Simulation'', By
    Sushanta Kumar Mandal, T K Bhattacharya, Ashudeb
    Dutta, International conference on Computer and
    Devices for Communication, CODEC-06, 2006
  • ''Automatic Test Generation for Temporal Coverage
    Points using a Stochastic Tree Model'', By P P
    Chakrabarti, Pallab Dasgupta, A. Nandi, B.Pal
    ,VDAT, 2006
  • ''Automatic Test Pattern Generation for Board
    Level Testing of IEEE 1149.1 Compatible
    Systems'', By Amit Patra, Santosh Biswas, S
    Mukhopadhyay, Subrata Mandal, V Jaiswal, National
    Seminar on Electronics, Devices and Circuits
    2006, BITS Mesra, 2006
  • ''Concurrent Testing of Digital Circuits for
    Advanced Fault Models'', By Amit Patra, Santosh
    Biswas, S Mukhopadhyay, Pradipta Patra,IEEE DDECS
    2006, Czech Republic, 2006
  • ''Concurrent Testing of Digital Circuits for
    Non-Classical Fault Models Resistive Bridging
    Fault Model and n-Detect Test'', By Amit Patra,
    Santosh Biswas, S Mukhopadhyay, D Sarkar, IEEE
    European Test Symposium 2006, Southampton, UK,
    2006
  • ''CORDIC Based VLSI architecture for Hanning and
    Hamming windowing for real time spectral
    analysis.'', By A S Dhar, Kailash Chandra Ray ,
    International Conference on Computer and Devices
    for Communications(CODEC2006),Kolkata,India, 2006
  • ''Design and Analysis of a VHF OTA-C Cell for
    Optimum Phase Response'', By Pradip Mandal,
    Kshitij Yadav, IEEE Asia Pacific Conference on
    Circuits and Systems (APCCAS), Singapore, 2006
  • ''Design of a 1 V Low Power 900 MHz QVCO'', By T
    K Bhattacharya, Ashudeb Dutta, Prabir Saha, IEEE
    VLSI Design Conference, India, 2006
  • ''Detecting faults at the time they occur'', By P
    P Chakrabarti, Pallab Dasgupta, A. Kumar, S.
    Das,VDAT, 2006
  • ''Development of a Wireless Integrated Toxic and
    Explosive MEMS Based Gas Sensor'', By T K
    Bhattacharya, Debashis Mandal, Shreyas Sen, S. K.
    Lahiri, IEEE International Conference on VLSI
    Design Embedded Systems, 2006
  • ''Diagnosability Analysis of Real Time Hybrid
    Systems'', By Amit Patra, Santosh Biswas, S
    Mukhopadhyay, D Sarkar, IEEE ICIT 2006, IIT
    Mumbai, 2006
  • ''Discovering the Input Assumptions in
    Specification Refinement Coverage'', By P P
    Chakrabarti, Pallab Dasgupta, P. Basu, S. Das,
    ASPDAC, 2006
  • ''Exact method for estimating Expected Settling
    Power in Sequential Circuits'', By P P
    Chakrabarti, Pallab Dasgupta, D. Chakraborty,
    VDAT 2006, 2006
  • ''Fairness of Transitions in Diagnosability
    Analysis of Hybrid Systems'', By Amit Patra,
    Santosh Biswas, S Mukhopadhyay, D Sarkar, C
    Karfa, H Kanwar, American Control Conference,
    USA, 2006
  • ''Fairness of Transitions in Diagnosability
    Analysis of Hybrid Systems'', By Amit Patra,
    Santosh Biswas, S Mukhopadhyay, Chandan Karfa, D.
    Sarkar, H. kanwar, American Control Conference,
    2006 (ACC 2006), 2006
  • ''Formal Verification of Power Scheduling
    Policies for Battery Powered Mobile '', By P P
    Chakrabarti, Pallab Dasgupta, Sayak Ray, IEEE
    INDICON 2006, Sept. 15-17, 2006, New Delhi,
    India, 2006
  • ''Generation of Expander Graphs Using Cellular
    Automata and its Applications to Cryptography'',
    By Debdeep Mukhopadhyay, D. Roychowdhury, 7th
    International Conference on Cellular Automata for
    Research and Industry (ACRI 2006), 20-23
    September 2006, Perpignan, France, 2006
  • ''Instruction-Set-Extension Exploration using
    Decomposable Heuristic Search'', By P P
    Chakrabarti, Pallab Dasgupta, Samik. Das, VLSI,
    2006

29
2006 List of Conference Papers Contd…
  • 'Property Driven Test Generation in Absence of
    Direct Interface'', By P P Chakrabarti, Pallab
    Dasgupta, Bhaskar Pal, IEEE INDICON, 2006
  • ''R6Crypt A New Cryptosystem for Handheld
    Devices'', By Debdeep Mukhopadhyay, D
    Roychowdhury, Proceedings of International
    Conference on Computer \ Communication
    Engineering, 2006
  • ''Strategy based Layout Automation of Analog Test
    Structures'', By Santosh Biswas, Samrat Mondal,
    Devjyoti Patra, Subrat Panda, National Seminar on
    Devices, Circuits and Communication, 2006
  • ''Synthesis of System Verilog Assertions'', By P
    P Chakrabarti, Pallab Dasgupta, S. Das, R.
    Mohanty, DATE, 2006
  • ''Test Generation Games from Formal
    Specifications'', By P P Chakrabarti, Pallab
    Dasgupta, A. Banerjee, B.Pal, S. Das, A. Kumar,
    DAC, 2006
  • ''Verification of Scheduling in High-level
    Synthesis'', By Chandan Karfa, Chittaranjan
    Mandal, Dipankar Sarkar, Satyam Pentakota, Chris
    Reade, In IEEE Computer Society Annual Symposium
    on VLSI (ISVLSI 06), 2006
  • ''What lies between Design Intent Coverage and
    Model Checking?'', By P P Chakrabarti, Pallab
    Dasgupta, S. Das, P. Basu, DATE, 2006
  • ''Wide-band Lumped Element Compact CAD Model of
    Si-Based Planar Spiral Inductor for RFIC
    Design'', By Sushanta Kumar Mandal, Arijit
    De,Amit Patra, Shamik Sural, 19th International
    Conference on VLSI Design, 2006
  • ''A Formal Verification Method of Scheduling in 
    High-level Synthesis'', By Chandan Karfa,
    Chittaranjan  Mandal,  Dipankar Sarkar, Chris
    Reade ,In 7th IEEE International  Symposium on
    Quality Electronic Design (ISQED?06),  2006    
      
  • ''Fairness of Transitions in Diagnosability
    Analysis of Hybrid Systems'', By Amit Patra,
    Santosh Biswas, S  Mukhopadhyay, Chandan Karfa,
    D. Sarkar, H. kanwar , American Control 
    Conference, 2006 (ACC 2006), 2006       
  • ''Verification of Scheduling in High-level 
    Synthesis'', By Chandan Karfa, Chittaranjan 
    Mandal,  Dipankar Sarkar, Satyam Pentakota, Chris
    Reade, In IEEE Computer Society Annual  
    Symposium  on VLSI (ISVLSI?06), 2006       
  • ''Automatic Test Pattern Generation for Board 
    Level Testing of IEEE 1149.1 Compatible
    Systems'', By Amit Patra, Santosh Biswas, S 
    Mukhopadhyay, Subrata Mandal, V Jaiswal,  
    National Seminar on Electronics, Devices and 
    Circuits  2006, BITS Mesra, 2006       
      ''Concurrent Testing of Digital Circuits  for 
    Advanced Fault Models'', By Amit Patra, Santosh
    Biswas, S  Mukhopadhyay, Pradipta Patra, IEEE
    DDECS 2006, Czech  Republic, 2006
  •    ''Concurrent Testing of Digital Circuits 
    for  Non-Classical Fault Models Resistive
    Bridging  Fault  Model and n-Detect Test'', By
    Amit Patra, Santosh Biswas, S  Mukhopadhyay, D
    Sarkar,  IEEE European Test  Symposium 2006,
    Southampton, UK, 2006         ''Diagnosability
    Analysis of Real Time  Hybrid Systems'', By Amit
    Patra, Santosh Biswas, S  Mukhopadhyay, D Sarkar,
    IEEE ICIT 2006, IIT Mumbai, 2006 
  • ''Fairness of Transitions in  Diagnosability
    Analysis of Hybrid Systems'', By Amit Patra,
    Santosh Biswas, S  Mukhopadhyay, Chandan Karfa,
    D. Sarkar, H. kanwar , American  Control
    Conference, 2006 (ACC 2006), 2006       
  • ''Strategy based Layout Automation of   Analog 
    Test Structures'', By Santosh Biswas, Samrat
    Mondal,  Devjyoti Patra, Subrat Panda  ,National
    Seminar on Devices,  Circuits and Communication,
    2006       
  • "Performance Evaluation of MISISFET", By Angik
    Sarkar and T. K. Bhattacharyya, IEEE ICONN,
    Brisbane, (2006)

30
2006 List of Conference Papers Contd…
  • "PSO-based evolutionary optimization for
    black-box modeling of arbitrary shaped on-chip RF
    inductors", By R. Bhattachrya, A Joshi, T. K.
    Bhattacharyya, IEEE MTT Topical Meeting on
    Silicon Monolithic Integrated Circuits in RF
    Syatems, 2006. Digest of Papers. 2006 Pages
    103-106, USA, (2006)
  • "Sampled Analog Architecture for 2-D DCT", By
    Chintan Thakkar, Anindya Dhar, IEEE International
    Symposium on Circuits and Systems, Island of Kos,
    Greece, (2006)
  • "AND-OR/XOR based circuit synthesis for area
    minimization", By S. Chaudhury, T. Anish, and S.
    Chattopadhyay, CODEC-2006, Kolkata, (2006)
  • "Architectural design and implementation of a PC
    based ultrasound imaging system", By Bodhisatwa
    Majumdar, Joydeep Bhattacharyya, Aman Mediratta
    and Swapna Banerjee, International Conference on
    VLSI Design and Test symposium (VDAT 06), Goa,
    India, (2006)
  • "Design and Analysis of a VHF OTA-C Cell for
    Optimum Phase Response", By Kshitij Yadav and P.
    Mandal, IEEE Asia Pacific Conference on Circuits
    and Systems (APCCAS), Singapore, Dec.2006, (2006)
  • "A VHF OTA-C topology having low phase error with
    Gm tuning", By Kshitij Yadav and P. Mandal,
    ICCCAS, China, (2006)
  • "Development of a Wireless Integrated Toxic and
    Explosive MEMS Based Gas Sensor.", By T. K.
    Bhattacharyya, Shreyas Sen, Debashis Mandal, S.
    K. lahiri, IEEEVLSI 2006, Hydrabad, India (2006)
  • "An 8-bit, 3.8GHz Dynamic BiCMOS Comparator for
    High-Performance ADC", By Sanjoy Kumar Dey and S.
    Banerjee, 19th IEEE Int. conf. on VLSI Design
    (VLSI?06), Hyderabad, (2006)
  • "Max-supply selector using a supply voltage
    comparator", By P. Mandal, Athar Ali Khan and R.
    Pandey, Mixed Design of Integrated circuits and
    Systems, Poland, (2006)
  • "Micro fabrication of CMOS compatible Tunneling
    Accelerometer with sub ug Resolution", By T. K.
    Bhattacharyya., IndoJapan seminar on advanced
    manufaceturing science, Tokyo, Japan, (2006)
  • "A Dedicated Processor to Realize Inverse Radon
    Transform for CT Imaging", By Abhishek Mitra and
    Swapna Banerjee, International Conference on VLSI
    Design and Test symposium (VDAT 06), Goa, India,
    (2006)
  • "Synthesis of finite stste machines for low power
    and testability", By S. Chaudhury, J. Srinivasa
    Rao, and S. Chattopadhyay, IEEE Asia Pacific
    Conference on Circuits and Systems (APCCAS),
    Singapore, (2006)
  • "MISIS-FET A Device with an Advanced
    Dielectricstructure", By Angik Sarkar and T. K.
    Bhattacharyya, IEEE Conference Emerging
    Technologies- nanoelectronics, Singapore, (2006)
  • "Design of a 1 V Low Power 900 MHz QVCO", By
    Prabir K. Saha, Ashudeb Dutta, A. Patra, T. K.
    Bhattacharyya, IEEE VLSI 2006, Hyderabad, India,
    (2006)
  • "Development of Silicon and Quartz Based MEMS
    High Precision Accelerometers", By S. Kal,
    Indo-Chienese Workshop on MEMS Devices and
    Related Technologies, New Delhi, (2006)
  • "A Formal Approach for High Level Synthesis of
    Linear Analog Systems", By Soumya Pandit,
    Chittaranjan Mandal, Amit Patra, ACM/IEEE GLSVLI
    2006, USA, (2006)
  • "A Formal Verification Method of Scheduling in
    High-level Synthesis", By C. Karfa, C. Mandal, D.
    Sarkar, S. R. Pentakota and C. Reade, 7th
    International Symposium on Quality Electronic ??
    2006, ISQED ?06?, (2006)
  • "Built-in Self-Test for Flash Memory Embedded in
    SOC", By S. Banerjee, and D. R. Chowdhury, Third
    IEEE International Workshop on Electronic Design,
    Test and Applications, Malaysia, (2006)
  • "Concurrent Testing of Digital Circuits for
    Advanced Fault Models", By S. Biswas, S.
    Mukhopadhyay, A Patra and D Sarkar, IEEE DDECS
    2006, Czech Republic, (2006)

31
2006 List of Conference Papers Contd….
  • "Concurrent Testing of Digital Circuits for
    Advanced Fault Models", By S. Biswas, S.
    Mukhopadhyay, A Patra and D Sarkar, IEEE DDECS
    2006, Czech Republic, (2006)
  • "Concurrent Testing of Digital Circuits for
    Non-Classical Fault Models Resistive Bridging
    Fault Model and n-Detect Test", By S. Biswas, S.
    Mukhopadhyay, A. Patra and D. Sarkar, IEEE
    European Test Symposium 2006, Southampton, UK,
    (2006)
  • "High-level Synthesis of Linear Analog Systems",
    By Soumya Pandit, Chittaranjan Mandal, Amit
    Patra, CSI-EAIT, Calcutta, India, (2006)
  • "Improving the Performance of CAD Optimization
    Algorithms Using On-Line Meta-Level Control", By
    Sandip Aine, PP Chakrabarti, and Rajeev Kumar,
    VLSI Design 2006, Hyderabad, India, (2006)
  • "Instruction-Set-Extension exploration using
    Decomposable Heuristic Search", By S. Das, P.P.
    Chakrabarti, P. Dasgupta, VLSI Design, India,
    (2006)
  • "Verification of Scheduling in High-level
    Synthesis", By C. Karfa, C. Mandal D. Sarkar, S.
    R. Pentakota and C. Reade, IEEE Computer Society
    Annual Symposium on Emerging VLSI Technologies
    and Architectures (ISVLSI?06), Karlsruhe,
    Germany, (2006)
  • "A Fully Differential 11mW 10-bit 200MS/s Sample
    and Hold in 0.25u BiCOMOS Technology", By Surajit
    Sarkar, Arindrajit Ghosh and Swapna Banerjee,
    2006 IEEE Asia Pacific Conference on Circuits and
    Systems, Singapore, (2006)
  • FPGA implementation of an automobile pollution
    control system using a MEMS accelerometer", By R.
    T. Roushan, G. Saha, A. Boni and S. Kal, IEEE
    International conference on Industrial Technology
    (ICIT) 2006, Mumbai, (2006)
  • "An approach to reduce power by scan chain
    partitioning and flip-flop reordering", By P.
    Ghosh, B. B. Paul, and I. Sen Gupta, RETE-06,
    Kolkata, (2006)
  • "An Efficient Algorithm for scheduling
    verification", By Chandan Karfa, S R Pentakota,
    Chittaranjan mandal, Dipankar Sarkar, Chris
    Reade, CSI-EAIT, Calcutta, India(2006)
  • "An Efficient Scan tree design for compact test
    pattern set", By S. Banerjee, D. R. Chowdhury,
    and B. B. Bhattacharya, 19th International
    Conference on VLSI Design , Hyderabad, India
    (2006)
  • "An optical algorithm for register renaming a
    post compilation technique", By Sanjay
    Chatterjee, PP Chakrabarti, and rajeev Kumar, 9th
    VLSI Design Test Symposium (VDAT),
    Bangalore,(2006)
  • "Design and Analysis of a Robust and Efficient
    Block Cipher Using Cellular Automata", By P.
    Joshi, D. Mukhopadhyay and D. Roy Chowdhury,
    International Conference on Advanced Networking
    and Applications (AINA-06), Viena, Austria (2006)
  • "On Finding the Minimum Test set of a BDD-Based
    Circuit", By Gopal Paul, Bhargab B. Bhattacharya
    and Ajit Pal, ACM/IEEE Great Symposium on VLSI,
    USA, (2006)
  • "Routing-aware multi-scan chain optimization
    technique for low power testing", By B. B. Paul,
    R. Mukhopadhyay, S. Banerjee, and I Sen Gupta,
    International Conference on Computer and
    Communication Engg. (ICCCE'06), Kuala Lumpur,
    Malaysia (2006)
  • "Sizing for Low power", By A. Jana and A. Pal,
    International Conference on Computer and
    Communication Engg (ICCCE'06), Kualalampur,
    Malaysia (2006)
  • "Test generation games from Formal
    Specifications", By A. Banerjee, B. Pal, S. Das,
    A. Kumar, P. Dasgupta, Design Automation
    Conference, San Francisco (2006)
  • "What Lies between Design Intent Coverage and
    Model checking?", By S. Das, P. Basu, P.
    Dasgupta, P. P. Chakrabarti, design Automation
    and Test in Europe, Munich, Germani (2006)
  • "High Level Synthesis of Higher order Continuous
    Time State variable Filter with minimum
    sensitivity and hardware Count", By Soumya
    pandit, Chittaranjan Mandal, Amit Patra, DATE 06,
    Germany (2006)

BACK
32
2007 List of Journal Publication
  • ''Diagnosis of Delay-Deadline Failures in Real 
    Time Discrete Event Models'', By Amit Patra,
    Santosh Biswas, S  Mukhopadhyay, D Sarkar,  ISA
    Transactions,  2007
  • "Broad band behavioral modeling of on chip RE
    inductors and transformers", By R Bhattacharya
    and T K Bhattacharyya Microwave and Ptrical
    Technology Letters, vol-49 (9) 2212-2216 (2007)
  • "Secured Flipped Scan Chain Model for
    Crypto-architecture", By G. Sengar, D.
    Mukhopadhyay and D. RoyChowdhury, IEEE
    Transactions on CAD, Nov 2007, Volume 26, Issue
    11 pp 2080-2084.
  • "Hierarchical Verification of Galois Field
    Circuits", By D. Mukhopadhyay, G. Sengar, and D.
    RoyChowdhury, IEEE Transactions on CAD, Oct 2007,
    Volume 26, Issue 10, pp 1893-1898.
  • "An Efficient Scan Tree Design for Compact Test
    Pattern Set", By S. Banerjee, D.Roy Chowdhury,
    and B.B. Bhattacharya, IEEE Transactions on 
    Computer-Aided Design (CAD)of Integrated Circuits
    and Systems,.Volume 26, No 7, pp1331-1339,July
    2007.
  • "Design of active inductors in SiGe/SiGeC
    processes for RF applications", By A.
    Chakravorty, R. F. Scholz , B. Senapati, R. Garg,
    C. K. Maiti Int. J. RF Microwave CAE, vol-17,
    pp.455-468 (2007)
  • "New VLSI Architecture for Motion Estimation
    Algorithm", By V.S.K.Reddy and S. Sengupta
    International Journal of Computer and Information
    science and Engineering (IJCISE), vol-20,
    pp-162-165 (2007).
  • "On feasibility of a multiplier-less phase
    shifting scheme for digital phase modulation and
    its VLSI implementation", By R. Mahapatra, A. S.
    Dhar and D. Datta Int. J. Electronics vol. 94,
    pp.171-181 (2007)
  • ''ANN and PSO based Synthesis of On-Chip Spiral
    Inductors for RF ICs'' , By Sushanta Kumar
    Mandal, Shamik Sural and Amit Patra , IEEE
    Transactions on COMPUTER-AIDED DESIGN of
    Integrated Circuits and Systems (Accepted), 2007
  • "An Efficient Scan Tree Design for Compact Test
    pattern Set", By S. Banerjee, D.Roy Chowdhury and
    B. B. Bhattacharya, IEEE Transactions on
    Computer-Aided Design of Integrated Circuits and
    Systems, July 2007, V 26(7), pp1331-1339 (2007)
  • ''Broadband Scalable Model for Si-RF On-Chip
    Spiral Inductors with Substrate Eddy Current
    Effect'', By Sushanta Kumar Mandal, Shamik Sural
    and Amit Patra , International Journal of RF and
    Microwave Computer-Aided Engineering (Accepted),
    2007
  • ''BUSpec A Framework for generation of
    Verification aids for Standard Bus Protocol
    Specifications'', By P P Chakrabarti, Pallab
    Dasgupta, Bhaskar Pal, Ansuman Banerjee ,VLSI
    Journal, Elsevier, Vol 40, Issue 3, pp. 285-304,
    2007
  • ''Compact small signal modeling and PSO based
    input matching of a packaged CMOS LNA in
    Subthreshold region'', By T K Bhattacharya,
    Ashudeb Dutta, Kaushik Dasgupta, Microelectronics
    Journal ,vol-38, pp. 1050-1056 Elsevier, 2007
  • ''Event propagation for accurate circuit delay
    calculating using SAT'', By P P Chakrabarti,
    Pallab Dasgupta, Suchismita Roy,  ACM
    TODAES,vol-12, No.3, Article 36, 2007
  • ''Hardware Accelerated Constrained Random Test
    Generation'', By P P Chakrabarti, Pallab
    Dasgupta, Pradip Mandal, Bhaskar Pal, Arnab
    Sinha, Kaushik De ,  IET Computers and Digital
    Techniques, vol-1, issue4, pp. 423-433, 2007
  • ''Statistical Static Timing Analysis using
    Symbolic Event Propagation'', By P P Chakrabarti,
    Pallab Dasgupta, Arijit Mondal, IET Circuits,
    Device Systems, vol-1, issue4, pp. 283-291,
    2007
  • "A Graph Algorithm for Finding the Minimum Test
    Set of a BDD-based Circuit", By Gopal Paul,
    Bhargab B. Bhattacharya and Ajit Pal, ---accepted
    in Advances in Computer Science and Engineering
    Reports and Monographs - 2007 World Scientific
    Press vol. 2 pages 382-386.
  • "An Evolutionary Algorithm-Based Approach to
    Automated design of Analog and RF Circuits Using
    Adaptive Normalized Cost Function", By Abhishek
    Somani, Partha P. Chakraborty and Amit Patra,
    IEEE Transations on Evolutionary Computation,
    Vol. 11, No. 3, June 2007.

33
2007 List of Conference Papers
  • "7.95mW 2.4 GHz fully integrated CMOS integer N
    frequency synthesizer", By Debashis Mandal and T
    K Bhattacharyya., IEEE VLSI Design 2007.,
    Bangalore, (2007)
  • "A DFT Methodology for Detecting Bridging Faults
    in Reversible Circuits", By  Mayur Bubna, Nitin
    Goyal, Indranil Sengupta, Proc. of IEEE Tencon,
    Taipei, 2007.
  • "FPGA-Based Architecture for Block Matching
    Motion Estimation Algorithm", By V. S. K. Reddy
    and S. Sengupta, 11th Workd Multi-conference on
    Systemic, Cybernetics and Informatics
    WMSCI-2007, Orlando, Florida, (2007)
  • "Latency Optimized AES-Rijndael with Flexible
    Mode of Operation" By Monjur Alam, Santosh Ghosh,
    Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury and
    Indranil Sen Gutpa, VDAT 2007, pages 413-420,
    Kolkata, India, August 2007.
  • "Design and FPGA implementation of GF(p) Elliptic
    Curve Cryptosystem Accelerator Preventing Side
    Channel Attack", By S. Ghose, D. RoyChowdhury and
    I. Sengupta, 15th ACM/SIGDA International
    Symposium on Field-Programmable Gate Arrays,
    Monterey Beach Resort Monterey, California,
    February 18-20, 2007
  • "An Efficient Design of Cellular Automata based
    Cryptographically Robust One-Way Function", By D.
    Mukhopadhyay, P. Joshi and D.RoyChowdhury,
    Proceedings of 20th  International Conference on
    VLSI Design, 2007
  • "Reducing test-bus power consumption in Huffman
    coding based test data compression for SOCs", By
    C. Giri and S. Chattopadhyay, IEEE International
    Symposium on Circuits and Systems (ISCAS), New
    Orleans, USA, (2007)
  • "Low Power Sensor Node for a Wireless Sensor
    Network", By Akepati Sravan, Sujan Kundu.,20th
    International Conference on VLSI Design, January
    2007, Bangalore, India.
  • "Embedded Support Vector Machine Architectural
    Enhancements and Evaluation", By Dey S., Kedia M.
    and Basu A, 20th International Conference on
    VLSI  Design and 6th International Conference on
    Embedded Systems, 2007.
  • "Architectural Optimizations for Text to Speech
    Synthesis in Embedded Systems", By Dey S., Kedia
    M., Agarwal N. and Basu A.., 12th Asia and South
    Pacific Design Automation Conference, 2007.
  • "Static and Dynamic Power Minimization with Area
    Trade-off in Multiplexer Based Circuit
    Synthesis", By Sambhu. Nath. Pradhan, S.
    Chattopadhayay, Proc. IEEE VDAT-2007, Kolkata
  • "Designing Cellular Automata Structures using
    Quantum-Dot Cellular Automata", By Mayur Bubna,
    Subhra Mazumdar, Sudip Roy, Rajib Mall, Web
    Proceedings of 14th IEEE International Conference
    on High Performance Computing (HiPC 2007), Goa,
    India.
  • ''Hand-in-hand Verification of High-level 
    Synthesis'', By Chandan Karfa, Chittaranjan
    Mandal,  Dipankar Sarkar, Chris reade , 17th
    edition of ACM Great Lakes  Symposium  on VLSI
    (GLSVLSI) 2007.
  • ''Register Sharing Verification during  Data-path
    Synthesis'', By Chandan Karfa, Chittaranjan 
    Mandal,  Dipankar Sarkar, Chris Reade ,In IEEE
    International Conference on Computing Theory and
    Application,  2007
  • ''Verification of Data-path and Controller
    Generation Phase of High-level Synthesis'', By
    Chandan Karfa, Chittaranjan  Mandal,  Dipankar
    Sarkar , 15th  International Conference on
    Advanced Computing Communication, 2007 
  • ''A chaos-modulated ramp generator IC for
    flexible EMI reduction in voltage-mode controlled
    PWM buck converters'', By Amit Patra, Rupam
    Mukherjee, Soumitro Banerjee, International
    Symposium of Integrated Circuits, 2007

34
2007 List of Conference Papers Contd…
  • 'A Common Gate Distributed Amplifier with 17 dB
    Gain, 10 GHz Bandwidth using shunt series peaking
    amplification'', By T K Bhattacharya, Ashudeb
    Dutta, Sourish Haldar, International Conference
    on Ultra Wide-Band (IEEE ICUWB -07), 2007
  • ''A Low voltage, Low ripple on Chip Hybrid DC-DC
    Converter'', By Kaushik Bhattacharyya, Pradip
    Mandal, International Symposium on Integrated
    Circuits 2007(ISIC-2007), Singapore, 2007
  • ''A NEW APPROACH FOR TESTING OF DIGITAL MODULES
    IN MIXED SIGNAL VLSI CIRCUITS'', By Amit Patra,
    Santosh Biswas, S Mukhopadhyay, Rahul
    Bhattacharya,VLSI Design and Test, 2007
  • ''A New Pseudo-Boolean Satisfiability based
    approach to Power Mode Schedulability Analysis'',
    By P P Chakrabarti, Pallab Dasgupta, Sayak Ray,
    VLSI, 2007
  • ''An Algorithm for Resistance Extraction and
    Current Density Profiling of Lateral Power
    MOSFETs'', By Amit Patra, Baidurya Chatterjee,
    Syamantak Das, Samrat Ray , 11th IEEE VLSI Design
    and Test Symposium, 2007
  • ''ASIC Architecture for implementing blackman
    windowing for real time spectral analysis.'', By
    A S Dhar, Kailash Chandra Ray, International
    Conference on Signal processing,Communications
    and Networking(ICSCN2007),Chennai,India., 2007
  • ''Bounded Delay Timing Analysis Using Boolean
    Satisfiability'', By P P Chakrabarti, Pallab
    Dasgupta, Suchismita Roy, VLSI, 2007
  • ''Can Semi-Formal be made more Formal ?'', By P P
    Chakrabarti, Pallab Dasgupta, A. Banerjee, GMISL,
    2007
  • ''Formal Assertion based Verification in
    Industrial Setting'', By Pallab Dasgupta, Raj S.
    Mitra, Alok Jain, Jason Baumgartner,Tutorial
    presented at DAC, 2007
  • ''Hand-in-hand Verification of High-level
    Synthesis'', By Chandan Karfa, Chittaranjan
    Mandal, Dipankar Sarkar, Chris reade,17th edition
    of ACM Great Lakes Symposium on VLSI (GLSVLSI)
    2007.
  • ''Register Sharing Verification during Data-path
    Synthesis'', By Chandan Karfa, Chittaranjan
    Mandal, Dipankar Sarkar, Chris Reade,  In IEEE
    International Conference on Computing Theory and
    Application, 2007
  • ''Resistance Estimation of Lateral Power Arrays
    through Accurate Netlist Generation'', By Amit
    Patra, Syamantak Das, S Sural, Jyotirmoy Ghosh,
    IEEE International Symposium on Integrated
    Cicrcuits, 2007
  • ''Strengthening NLS against Crossword Puzzle
    Attack'', By Debojyoti Bhattacharya, Debdeep
    Mukhopadhyaya, Dhiman Saha, Dipanwita
    RoyChowdhury,12-th Australasian Conference on
    Information Security and Privacy, ACISP 2007,
    2007
  • ''Timing analysis of sequential circuits using
    symbolic event propagation'', By P P Chakrabarti,
    Pallab Dasgupta, Arijit Mondal, International
    Conference on Computing Theory and Applications,
    Platinum Jubilee conference of ISI Kolkata, 2007
  • ''Verification of Data-path and Controller
    Generation Phase of High-level Synthesis'', By
    Chandan Karfa, Chittaranjan Mandal, Dipankar
    Sarkar,  15th International Conference on
    Advanced Computing Communication, 2007  

BACK
35
2008 List of Journal Publication
  • ''An Equivalence Checking Method for Scheduling 
    Verification in High-level Synthesis'', By
    Chandan Karfa, Chittaranjan Mandal,  Dipankar
    Sarkar, Pramod Kumar  , IEEE  Transactions on
    COMPUTER-AIDED DESIGN of  Integrated  Circuits
    and Systems, vol-27, pp-556-569, March, 2008.
  • ''High throughput VLSI architecture for Blackman
    windowing in real time spectral analysis'', By A
    S Dhar, Kailash Chandra Ray, Journal of
    Computers, Vol.3, No.5,pp.54-59, May 2008.
  • ''Implementation of CMOS Low-power Integer-N
    Frequency Synthesizer for SOC Design'', By T K
    Bhattacharya, Debashis Mandal, Journal of
    Computers (JCP), VOL. 3, NO. 4,pp. 31-38, APRIL
    2008.
  • ''Satisfiability Models for Maximum Transition
    Power'', By P P Chakrabarti, Pallab Dasgupta,
    Suchismita Roy,  IEEE Transactions on VLSI
    Systems, accepted, 2008.
  • ''Accelerating Assertion Coverage with Adaptive
    Test-benches'', By Pallab Dasgupta, Bhaskar Pal,
    Ansuman Banerjee, Arnab Sinha, TCAD, accepted,
    2008.
  • "VLSI Architecture of a Cellular Automata based
    One-Way Function", By D. Mukhopadhyay, P. Joshi
    and D. RoyChowdhury, to be published  in Journal
    of Computers, Academy Publishers, 2008.
  • "Satisfiability Models for Maximum Transition
    Power", By Suchismita Roy, P.P. Chakrabarti, P.
    Dasgupta, IEEE Transactions on VLSI Systems,
    Volume 16, Issue 8, Pages 941-951, August 2008.
  • "Instrumenting AMS Assertion Verification on
    Commercial Platforms", By Rajdeep Mukhopadhyay,
    Subrat K. Panda, Pallab Dasgupta, John Gough,
    accepted in ACM Transactions on Design Automation
    of Electronic Systems (TODAES).
  • "Auxiliary State Machines Context-Sensitive
    Properties in Formal Verification", By Ansuman
    Banerjee, Pallab Dasgupta, P. P.
    Chakrabarti. accepted in ACM Transactions on
    Design Automation of Electronic Systems (TODAES).
  • "Design Intent Coverage Revisited", By Arnab
    Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan
    Das, Prasenjit Basu, P. P. Chakrabarti, accepted
    in ACM Transactions on Design Automation of
    Electronic Systems (TODAES).
  • "Accelerating Assertion Coverage with Adaptive
    Test-benches", By  Bhaskar Pal, Ansuman Banerjee,
    Arnab Sinha, Pallab Dasgupta, IEEE Transactions
    on CAD (TCAD), Volume 27, Issue 5, Pages967 -
    972, May 2008.
  • "Two-level AND-XOR Network Synthesis with
    Area-Power Trade-off", By S. N. Pradhan, S.
    Chattopadhayay, International Journal of Computer
    Science and Network Sequrity (IJCSNS), VOL.8
    No.9, September 2008.
  • "Synthesis of DSP Circuits for Low Power using
    Multiple-Vdd, Gate-level Sized and Optimal-Vt
    Library", By Sudip Roy and Arundhati Jana, 
    International Journal on Systemics, Cybernetics
    and Informatics (ISSN 0973-4864), pp. 37-41,
    July, 2008.

36
2008 List of Conference Papers
  • "A GF(p) Elliptic Curve Group Operator Resistant
    Against Side Channel Attacks", By Santosh Ghosh,
    Monjur Alam, Dipanwita Roy Chowdhury and Indranil
    Sen Gupta, To appear in Great Lake Symposium on
    VLSI (GLSVLSI'08), Orlando, Florida, May 2008,
  • "CheckSpec A Tool for Consistency and Coverage
    analysis of Assertion Specifications", By Ansuman
    Banerjee, K. Datta, Pallab Dasgupta. To appear in
    the proceedings of ATVA 2008.
  • "A Dynamic Assertion-based Verification Platform
    for Validation of UML designs", By Ansuman
    Banerjee, Sayak Ray, Pallab Dasgupta, P. P.
    Chakrabarti, S. Ramesh, P.V.V. Ganesan, To appear
    in the proceedings of ATVA 2008.
  • "Dynamic Assertion-based Verification Platform
    for UML Statecharts over Rhapsody", By Ansuman
    Banerjee, Sayak Ray, Pallab Dasgupta, P. P.
    Chakrabarti, S. Ramesh, P.V.V. Ganesan, To appear
    in IEEE TENCON 2008.
  • "Mode Based Functional Partitioning of Design
    Intent for Behavioral Modeling of Large AMS
    Circuits", By Rajdeep Mukhopadhyay, Antara Ain,
    S. K. Panda, Pallab Dasgupta, Siddhartha
    Mukhopadhyay, John Gough, Proceedings of VLSI
    Design and Test Symposium (VDAT) 2008.
  • "Raising the Level of Abstraction for the Timing
    Verification of System-on-Chips", By Rupsa
    Chakraborty and D. Roy Chowdhury, To appear in
    the International Conference ISVLSI 2008,
    Montpeiller, France, April 2008.
  • "Single Chip Encryptor / Decryptor Core
    Implementation of AES Algorithm", By Monjur Alam,
    Santosh Ghosh, Dipanwita Roy Chowdhury and
    Indranil Sen Gutpa, International Conference on
    VLSI Design (VLSID 2008), Hyderabad, India, IEEE
    Computer Society, January 2008.
  • ''A Fast Settling 100dB opamp in 180nm CMOS
    process with compensation based optimisation'',
    By Subho Chatterjee, T K Bhattacharya, Amal
    Kundu, VLSI Conference, 2008
  • "Three-level AND-OR-XOR Network Synthesis A GA
    Based Approach", By S.. N. Pradhan, M. Tilak
    Kumar and S. Chattopadhyay, Proc. IEEE APCCAS-08.
  • "Power-gated FSM Synthesis Integrating
    Partitioning and State Assignment", By M. Tilak
    Kumar, S. N. Pradhan and S. Chattopadhyay, Proc.
    IEEE TENCON-08.
  • "AND-XOR Network Synthesis with Area-Power
    Trade-off", By S. N. Pradhan and S.
    Chattopadhyay, in Proc. IEEE ICIIS.
  • "Artificial Intelligence Approach to Test Vector
    Reordering for Dynamic Power Reduction during
    VLSI Testing", By Sudip Roy, Ajit Pal, Indranil
    Sengupta, Proceedings of the IEEE TENCON 2008,
    Hyderabad, November 19-21, 2008.
  • "Impact of Runtime Leakage Reduction Techniques
    on Delay and Power Sensitivity under Effective
    Channel Length Variations", By Sudip Roy,Ajit
    Pal, Proceedings of the IEEE TENCON 2008,
    Hyderabad, November 19-21, 2008.
  • "Why to use Dual-Vt, if Single-Vt serves the
    purpose better under Process Parameter
    Variations?", By Sudip Roy,Ajit Pal, Proceedings
    of the Eleventh Euromicro conference on Digital
    System Design (DSD 2008), pp. 282-287, Italy,
    September 3-5, 2008.
  • "An Efficient Greedy Approach to PLA Folding", By
    Mayur Bubna, Naresh Shenoy, Santanu
    Chattopadhyay, IEEE International Symposium on
    Circuits and Systems (ISCAS), 2008.

37
2008 List of Conference Papers Contd…
  • ''A Low Voltage, Low Ripple, on Chip, Dual
    Switch-Capacitor Based Hybrid DC-DC Converter'',
    By Kaushik Bhattacharyya, Pradip Mandal,  21st
    International Conference On VLSI Design (VLSI
    Design 2008), Hyderabad, India, 2008
  • "A Layout Aware Physical Design Method for QCA
    Circuits", By Mayur Bubna, Sudip Roy, Naresh
    Shenoy, Subhra Mazumdar, accepted at ACM Great
    La
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