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Lab 1 and 2: Digital System Design Using Verilog

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Lab 1 and 2: Digital System Design Using Verilog Ming-Feng Chang CSIE, NCTU Introduction Objectives Understand the design methodologies using Verilog Target audience ... – PowerPoint PPT presentation

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Title: Lab 1 and 2: Digital System Design Using Verilog


1
Lab 1 and 2 Digital System Design Using Verilog
  • Ming-Feng Chang
  • CSIE, NCTU

2
Introduction
  • Objectives
  • Understand the design methodologies using Verilog
  • Target audience
  • have basic digital circuits design concept
  • use Verilog to design digital systems
  • Verilog description for logic synthesis
  • NOT in the talk
  • a full coverage of Verilog
  • use Verilog for quick behavioral modeling

3
  • Contents
  • Verilog HDL
  • structured modeling
  • RTL modeling
  • Example combinational circuits
  • structured description (net-list)
  • RTL
  • Example sequential circuits
  • RTL
  • FSM
  • combinational circuits
  • sequential circuits

4
Verilog history
  • Gateway Design Automation
  • Phil Moorby in 1984 and 1985
  • Verilog-XL, "XL algorithm", 1986
  • a very efficient method for doing gate-level
    simulation
  • Verilog logic synthesizer, Synopsys, 1988
  • the top-down design methodology is feasible
  • Cadence Design Systems acquired Gateway
  • December 1989
  • a proprietary HDL

5
  • Open Verilog International (OVI), 1991
  • Language Reference Manual (LRM)
  • making the language specification as
    vendor-independent as possible.
  • The IEEE 1364 working group, 1994
  • to turn the OVI LRM into an IEEE standard.
  • Verilog became an IEEE standard
  • December, 1995.

6
Hardware Description Languages
  • The functionality of hardware
  • concurrency
  • timing controls
  • The implementation of hardware
  • structure
  • net-list
  • ISP
  • C. Gordon Bell and Alan Newell at Carnegie Mellon
    University, 1972
  • RTL (register transfer level)

7
Different Levels of Abstraction
  • Algorithmic
  • the function of the system
  • RTL
  • the data flow
  • the control signals
  • the storage element and clock
  • Gate
  • gate-level net-list
  • Switch
  • transistor-level net-list

8
Verilog for Digital System Design
  • Structural description
  • net-list using primitive gates and switches
  • continuous assignment using Verilog operators
  • RTL
  • functional description
  • timing controls and concurrency specification
  • procedural blocks (always and initial)
  • registers and latches
  • C timing controls concurrency
  • An HDL to specify your design

9
Hierarchical structure
  • Represent the hierarchy of a design
  • modules
  • the basic building blocks
  • ports
  • the I/O pins in hardware
  • input, output or inout

10
Modules
  • The principal design entity

Module Name Port List
Definitions Ports, Wire, Reg, Parameter
Module Instatiations
Module Statements Constructs
11
Examples
  • 4-bit adder
  • module add4 (s,c3,ci,a,b)
  • input 30 a,b // port declarations
  • input ci
  • output 30 s // vector
  • output c3
  • wire 20 co
  • add a0 (co0, s0, a0, b0, ci)
  • add a1 (co1, s1, a1, b1, co0)
  • add a2 (co2, s2, a2, b2, co1)
  • add a3 (c3, s3, a3, b3, co2)
  • endmodule

a0
a1
a2
a3
c3
ci
12
  • A full-adder
  • module add (co, s, a, b, c)
  • input a, b ,c
  • output co, s
  • xor (n1, a, b)
  • xor (s, n1, c)
  • nand (n2, a, b)
  • nand (n3,n1, c)
  • nand (co, n3,n2)
  • endmodule

13
Data types
  • Net
  • physical wire between devices
  • the default data type
  • used in structural modeling and continuous
    assignment
  • types of nets
  • wire, tri default
  • wor, trior wire-ORed
  • wand, triand wire-ANDed
  • trireg with capacitive storage
  • tri1 pull high
  • tri0 pull low
  • supply1 power
  • supply0 ground

14
  • Reg
  • variables used in RTL description
  • a wire, a storage device or a temporary variable
  • reg unsigned integer variables of varying bit
    width
  • integer 32-bit signed integer
  • real signed floating-point
  • time 64-bit unsigned integer
  • Parameters
  • run-time constants

15
Special Language Tokens
  • ltidentifiergt System tasks and functions
  • time
  • stop
  • finish
  • monitor
  • ltdelay specificationgt
  • used in
  • gate instances and procedural statements
  • unnecessary in RTL specification

16
Modeling Structures
  • Net-list
  • structural description for the top level
  • Continuous assignments (combination circuits)
  • data flow specification for simple combinational
  • Verilog operators
  • Procedural blocks (RTL)
  • always and initial blocks
  • allow timing control and concurrency
  • C-like procedure statements
  • primitives (truth table, state transition table)
  • function and task (function and subroutine)

17
Gate-Level Modeling
  • Net-list description
  • built-in primitives gates
  • A full-adder
  • module add (co, s, a, b, c)
  • input a, b ,c
  • output co, s
  • xor (n1, a, b)
  • xor (s, n1, c)
  • nand (n2, a, b)
  • nand (n3,n1, c)
  • nand (co, n3,n2)
  • endmodule

18
Verilog Primitives
  • Basic logic gates only
  • and
  • or
  • not
  • buf
  • xor
  • nand
  • nor
  • xnor
  • bufif1, bufif0
  • notif1, notif0

19
Primitive Pins Are Expandable
  • One output and variable number of inputs
  • not and buf
  • variable number of outputs but only one input

nand (y, in1, in2)
nand (y, in1, in2, in3)
nand (y, in1, in2, in3, in4)
20
Continuous Assignments
  • Describe combinational logic
  • Operands operators
  • Drive values to a net
  • assign out ab // and gate
  • assign eq (ab) // comparator
  • wire 10 inv in // inverter with delay
  • wire 70 c ab // 8-bit adder
  • Avoid logic loops
  • assign a b a
  • asynchronous design

21
Operators
  • concatenation
  • - /
  • arithmetic
  • modulus
  • gt gt lt lt
  • relational
  • ! logical NOT
  • logical AND
  • logical OR
  • logical equality
  • ! logical inequality
  • ? conditional
  • bit-wise NOT
  • bit-wise AND
  • bit-wise OR
  • bit-wise XOR
  • bit-wise XNOR
  • reduction AND
  • reduction OR
  • reduction NAND
  • reduction NOR
  • reduction XOR
  • reduction XNOR
  • ltlt shift left
  • gtgt shift right

22
  • Logical, bit-wise and unary operators
  • a 1011 b 0010
  • logical bit-wise unary
  • a b 1 a b 1011 a 1
  • a b 1 a b 0010 a 0
  • Conditional operator
  • assign z (s1,s0 2'b00) ? IA
  • (s1,s0 2'b01) ? IB
  • (s1,s0 2'b10) ? IC
  • (s1,s0 2'b11) ? ID
  • 1'bx
  • assign s (op ADD) ? ab a-b

23
Operator Precedence
  • bit-select or part-select
  • ( ) parentheses
  • !, logical and bit-wise negation
  • , , , , , , reduction operators
  • , - unary arithmetic
  • concatenation
  • , /, arithmetic
  • , - arithmetic
  • ltlt, gtgt shift
  • gt, gt, lt, lt
  • relational
  • , ! logical equality
  • bit-wise AND
  • , ,
  • bit-wise XOR and XNOR
  • bit-wise OR
  • logical AND
  • logical OR
  • ? conditional

24
RTL Modeling
  • Describe the system at a high level of
    abstraction
  • Specify a set of concurrently active procedural
    blocks
  • procedural blocks digital circuits
  • Procedural blocks
  • initial blocks
  • test-fixtures to generate test vectors
  • initial conditions
  • always blocks
  • can be combinational circuits
  • can imply latches or flip-flops

25
  • Procedural blocks have the following components
  • procedural assignment statements
  • timing controls
  • high-level programming language constructs

26
RTL Statements
  • Procedural and RTL assignments
  • reg integer
  • out a b
  • begin . . . end block statements
  • group statements
  • if. . . else statements
  • case statements
  • for loops
  • while loops
  • forever loops
  • disable statements
  • disable a named block

27
Combinational Always Blocks
  • A complete sensitivity list (inputs)
  • always _at_(a or b or c)
  • f ac bc
  • Simulation results
  • always _at_(a or b)
  • f ac bc
  • Parentheses
  • always _at_(a or b or c or d)
  • z a b c d // z (ab) (cd)

28
Sequential Always Blocks
  • Inferred latches (Incomplete branch
    specifications)
  • module infer_latch(D, enable, Q)
  • input D, enable
  • output Q
  • reg Q
  • always _at_ (D or enable) begin
  • if (enable)
  • Q lt D
  • end
  • endmodule
  • the Q is not specified in a branch
  • a latch like 74373

29
Combinational Circuit Design
  • Outputs are functions of inputs
  • Examples
  • MUX
  • decoder
  • priority encoder
  • adder

inputs
Outputs
comb. circuits
30
Multiplexor
  • Net-list (gate-level)
  • module mux2_1 (out,a,b,sel)
  • output out
  • input a,b,sel
  • not (sel_, sel)
  • and (a1, a, sel_)
  • and (b1, b, sel)
  • or (out, a1, b1)
  • endmodule

31
Multiplexor
  • Continuous assignment
  • module mux2_1 (out,a,b,sel)
  • output out
  • input a,b,sel
  • assign out (asel)(bsel)
  • endmodule
  • RTL modeling
  • always _at_(a or b or sel)
  • if(sel)
  • out b
  • else
  • out a

32
Multiplexor
  • 4-to-1 multiplexor
  • module mux4_1 (out, in0, in1, in2, in3, sel)
  • output out
  • input in0,in1,in2,in3
  • input 10 sel
  • assign out (sel 2'b00) ? in0
  • (sel 2'b01) ? in1
  • (sel 2'b10) ? in2
  • (sel 2'b11) ? in3
  • 1'bx
  • endmodule

33
  • module mux4_1 (out, in, sel)
  • output out
  • input 30 in
  • input 10 sel
  • reg out
  • always _at_(sel or in) begin
  • case(sel)
  • 2d0 out in0
  • 2d1 out in1
  • 2d2 out in2
  • 2d3 out in3
  • default 1bx
  • endcase
  • end
  • endmodule

out insel
34
Decoder
  • 3-to 8 decoder with an enable control
  • module decoder(o,enb_,sel)
  • output 70 o
  • input enb_
  • input 20 sel
  • reg 70 o
  • always _at_ (enb_ or sel)
  • if(enb_)
  • o 8'b1111_1111
  • else
  • case(sel)
  • 3'b000 o 8'b1111_1110
  • 3'b001 o 8'b1111_1101
  • 3'b010 o 8'b1111_1011
  • 3'b011 o 8'b1111_0111
  • 3'b100 o 8'b1110_1111
  • 3'b101 o 8'b1101_1111
  • 3'b110 o 8'b1011_1111
  • 3'b111 o 8'b0111_1111
  • default o 8'bx
  • endcase
  • endmodule

35
Priority Encoder
  • always _at_ (d0 or d1 or d2 or d3)
  • if (d3 1)
  • x,y,v 3b111
  • else if (d2 1)
  • x,y,v 3b101
  • else if (d1 1)
  • x,y,v 3b011
  • else if (d0 1)
  • x,y,v 3b001
  • else
  • x,y,v 3bxx0

36
Parity Checker
  • module parity_chk(data, parity)
  • input 07 data
  • output parity
  • reg parity
  • always _at_ (data)
  • begin check_parity
  • reg partial
  • integer n
  • partial data0
  • for ( n 0 n lt 7 n n 1)
  • begin
  • partial partial datan
  • end
  • parity lt partial
  • end
  • endmodule

37
Adder
  • RTL modeling
  • module adder(c,s,a,b)
  • output c
  • output 70 s
  • input 70 a,b
  • assign c,s a b
  • endmodule
  • Logic synthesis
  • CLA adder for speed optimization
  • ripple adder for area optimization

38
Tri-State
  • The value z
  • always _at_ (sela or a)
  • if (sela)
  • out a
  • else
  • out 1bz
  • Another block
  • always _at_(selb or b)
  • if(selb)
  • out b
  • else
  • out 1bz

assign out (sela)? a 1bz
39
  • Registers (Flip-flops) are implied
  • _at_(posedge clk) or _at_(negedge clk)
  • a positive edge-triggered D flip-flop
  • always _at_ (posedge clk)
  • q d

40
Procedural Assignments
  • Blocking assignments
  • always _at_(posedge clk) begin
  • rega data
  • regb rega
  • end
  • Non-blocking assignments
  • always _at_(posedge clk) begin
  • regc lt data
  • regd lt regc
  • end

41
Sequential Circuit Design
Outputs
Inputs
Combinational circuit
Memory elements
  • a feedback path
  • the state of the sequential circuits
  • the state transition
  • synchronous circuits
  • asynchronous circuits

42
  • Examples
  • D flip-flop
  • D latch
  • register
  • shifter
  • counter
  • pipeline
  • FSM

43
Flip-Flop
  • Synchronous clear
  • module d_ff (q,d,clk,clr_)
  • output q
  • input d,clk,clr_
  • reg q
  • always _at_ (posedge clk)
  • if (clr_) q 0
  • else q d
  • endmodule
  • Asynchronous clear
  • always _at_ (posedge clk or negedge clr_)
  • if (clr_) q 0
  • else q d

44
Register
  • module register (q,d,clk,clr_, set_)
  • output 70 q
  • input 70 d
  • input clk,clr_, set_
  • reg 70 q
  • always _at_ (posedge clk or negedge clr_ or negedge
    set_)
  • if (clr_)
  • q 0
  • else if (set_)
  • q 8b1111_1111
  • else
  • q d
  • endmodule

45
D Latches
  • D latch
  • always _at_ (enable or data)
  • if (enable)
  • q data
  • D latch with gated asynchronous data
  • always _at_ (enable or data or gate)
  • if (enable)
  • q data gate

46
  • D latch with gated enable
  • always _at_ (enable or d or gate)
  • if (enable gate)
  • q d
  • D latch with asynchronous reset
  • always _at_ (reset or data or gate)
  • if (reset)
  • q 1b0
  • else if(enable)
  • q data

47
Shifter
  • module shifter (so,si,d,clk,ld_,clr_)
  • output so
  • input 70 d
  • input si,clk,ld_,clr_ // asynchronous clear and
    synchronous load
  • reg 70 q
  • assign so q7
  • always _at_ (posedge clk or negedge clr_)
  • if (clr_)
  • q 0
  • else if (ld_)
  • q d
  • else
  • q70 q60,si
  • endmodule

d
ld_
so
si
shifter
clk
48
Counter
  • module bcd_counter(count,ripple_out,clr,clk)
  • output 30 count
  • output ripple_out
  • reg 30 count
  • input clr,clk
  • wire ripple_out (count 4'b1001) ? 01 //
    combinational
  • always _at_ (posedge clk or posedge clr) //
    combinational sequential
  • if (clr)
  • count 0
  • else if (count 4'b1001)
  • count 0
  • else
  • count count 1
  • endmodule

49
Memory
  • module memory (data, addr, read, write)
  • input read, write
  • input 40 addr
  • inout 70 data
  • reg 70 data_reg
  • reg 70 memory 08'hff
  • parameter load_file "cput1.txt"
  • assign data (read) ? memory addr 8'hz
  • always _at_ (posedge write)
  • memoryaddr data
  • initial
  • readmemb (load_file, memory)
  • endmodule

50
Finite State Machine
  • Moore model
  • Mealy model

next state
current state
inputs
comb. circuit
memory elements
comb. circuit
outputs
next state
current state
inputs
comb. circuit
memory elements
comb. circuit
outputs
51
Inefficient Description
  • module count (clock, reset, and_bits, or_bits,
    xor_bits)
  • input clock, reset
  • output and_bits, or_bits, xor_bits
  • reg and_bits, or_bits, xor_bits
  • reg 20 count
  • always _at_(posedge clock) begin
  • if (reset)
  • count 0
  • else
  • count count 1
  • and_bits count
  • or_bits count
  • xor_bits count
  • end
  • endmodule

52
  • Six implied registers

53
Efficient Description
  • Separate combinational and sequential circuits
  • module count (clock, reset, and_bits, or_bits,
    xor_bits)
  • input clock, reset
  • output and_bits, or_bits, xor_bits
  • reg and_bits, or_bits, xor_bits
  • reg 20 count
  • always _at_(posedge clock) begin
  • if (reset)
  • count 0
  • else
  • count count 1
  • end
  • // combinational circuits
  • always _at_(count) begin
  • and_bits count
  • or_bits count
  • xor_bits count
  • end
  • endmodule

54
  • Three registers are used

55
Mealy Machine Example
  • module mealy (in1, in2, clk, reset,out)
  • input in1, in2, clk, reset
  • output out
  • reg current_state, next_state, out
  • // state flip-flops
  • always _at_(posedge clk or negedge reset)
  • if (!reset)
  • current_state 0
  • else
  • current_state next_state
  • // combinational next-state and outputs
  • always _at_(in1 or in2 or current_state)
  • case (current_state)
  • 0 begin
  • next_state 1
  • out 1'b0
  • end
  • 1 if (in1) begin
  • next_state 1'b0
  • out in2
  • end
  • else begin
  • next_state 1'b1
  • out !in2
  • end
  • endcase
  • endmodule

56
Pipelines
  • An example
  • assign n_sum ab
  • assign p sum d_c
  • // plus D flip-flops
  • always _at_ (posedge clk)
  • sum n_sum

flip- flops
comb. circuits
flip- flops
comb. circuits
flip- flops
comb. circuits
a
n-sum
Dff
sum
b
out
p
Dff
Dff
c
d_c
57
A FSM Example
Traffic Light Controller
Picture of Highway/Farmroad Intersection
58
Specifications
Traffic Light Controller
? Tabulation of Inputs and Outputs
Input Signal reset C TS TL Output Signal HG, HY,
HR FG, FY, FR ST
Description place FSM in initial state detect
vehicle on farmroad short time interval
expired long time interval expired Description as
sert green/yellow/red highway lights assert
green/yellow/red farmroad lights start timing a
short or long interval
? Tabulation of Unique States Some light
configuration imply others
Description Highway green (farmroad red) Highway
yellow (farmroad red) Farmroad green (highway
red) Farmroad yellow (highway red)
State S0 S1 S2 S3
59
  • The block diagram

HR HG HY FR FG FY
FFs
Comb. circuits
Comb. circuits
C
state
n_state
TS
  • TL

60
State transition diagram
TL C
Reset
S0 HG S1 HY S2 FG S3 FY
S0
TLC/ST
TS/ST
TS
S1
S3
TS
TS/ST
TL C/ST
S2
TL C
61
Verilog Description
  • module traffic_light(HG, HY, HR, FG, FY, FR,ST_o,
  • tl, ts, clk, reset, c)
  • output HG, HY, HR, FG, FY, FR, ST_o
  • input tl, ts, clk, reset, c
  • reg ST_o, ST
  • reg01 state, next_state
  • parameter EVEN 0, ODD1
  • parameter S0 2'b00, S12'b01, S22'b10,
    S32'b11
  • assign HG (state S0)
  • assign HY (state S1)
  • assign HR ((state S2)(state S3))
  • assign FG (state S2)
  • assign FY (state S3)
  • assign FR ((state S0)(state S1))

62
  • // flip-flops
  • always_at_ (posedge clk or posedge reset)
  • if(reset) // an asynchronous reset
  • begin
  • state S0
  • ST_o 0
  • end
  • else
  • begin
  • state next_state
  • ST_o ST
  • end

63
  • always_at_ (state or c or tl or ts)
  • case(state) // state transition
  • S0
  • if(tl c)
  • begin
  • next_state S1
  • ST 1
  • end
  • else
  • begin
  • next_state S0
  • ST 0
  • end

TL C
Reset
S0
TLC/ST
TS/ST
TS
S1
S3
TS
TS/ST
TL C/ST
S2
TL C
64
  • S1
  • if (ts) begin
  • next_state S2
  • ST 1
  • end
  • else begin
  • next_state S1
  • ST 0
  • end
  • S2
  • if(tl !c) begin
  • next_state S3
  • ST 1
  • end
  • else begin
  • next_state S2
  • ST 0
  • end

TL C
Reset
S0
TLC/ST
TS/ST
TS
S1
S3
TS
TS/ST
TL C/ST
S2
TL C
65
  • S3
  • if(ts)
  • begin
  • next_state S0
  • ST 1
  • end
  • else
  • begin
  • next_state S3
  • ST 0
  • end
  • endcase
  • endmodule

TL C
Reset
S0
TLC/ST
TS/ST
TS
S1
S3
TS
TS/ST
TL C/ST
S2
TL C
66
Efficient Modeling Techniques
  • Separate combinational and sequential circuits
  • always know your target circuits
  • Separate structured circuits and random logic
  • structured data path, XORs, MUXs
  • random logic control logic, decoder, encoder
  • Use parentheses control complex structure
  • .....

67
Conclusions
  • Verilog modeling
  • structured modeling
  • continuous assignment
  • RTL modeling
  • Design digital systems
  • separate combinational and sequential description
  • always keep your target circuits in mind

68
Reference
  • Verilog-XL Training Manual, CIC
  • Logic Synthesis Design Kit, CIC
  • HDL Compiler for Verilog Reference Manual,
    Synopsys
  • Synthesis Application Notes, Synopsys Online
    Documentation
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