LOWPOWER TEST PATTERN GENERATOR DESIGN for BIST via NONUNIFORM CELLULAR AUTOMATA Hrevren Kili Comput

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LOW-POWER TEST PATTERN GENERATOR DESIGN for BIST
via NON-UNIFORM CELLULAR AUTOMATAHürevren
KiliçComputer Engineering DepartmentAtilim
University, Ankara, Turkeyhurevren_at_atilim.edu.tr
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Table of Contents

• Introduction
• Non-Uniform Cellular Automata (NUCA)
• The Algorithm
• Experimental Results
• Conclusion

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Introduction

• Built-In Self-Test a design-for-test technique
• Typical BIST design steps
• On-chip test pattern generation,
• Application of patterns to the Circuit Under Test
  (CUT),
• Analysis of CUT responses via on-chip Output
  Response Analyzer (ORA),
• Making decision whether the chip is faulty or
  not.

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Introduction

• Our focus On step 1, i.e.efficient TPG design
• Design Objectives
• Minimal Hw Size (area, component)
• Minimal Testing Time
• High Fault Coverage
• Low-Power Consumption
• Test-per-clock scheme.

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Introduction

• Important, when total package power consumption
  is around its critical limits !!!
• Post-processing. Refined TPG unit.
• Statistically, low activity production at the
  primary inputs of the CUT results in reduction at
  CUTs power consumption Corno et.al., 2000

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Process Description
Test Vector Sequence (mxn matrix)
n Independent Minimum Set Covering Problem
Conversion Algorithm
Optimization Package
Solutions to the generated problems
Solutions Merger Program
Designed TPG
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Non-Uniform Cellular Automata

• Automata Networks (by John Von Neumann)
• Locally interconnected large set of cells (or
  components)
• Mutual interaction between cells
• Evolve at discrete time steps
• State values (like 0, 1)

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Non-Uniform Cellular Automata

• The inverse problem
• Given a global effect on state space
  configurations, determine local rule(s) that can
  produce the effect
• Why ?
• For better understanding the system behaviors
• To obtain cost-effective minimal designs

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Non-Uniform Cellular Automata

• Definition 1
• A trajectory is a matrix Zmxn where m the
  number global automata network states (m1) and n
  the number of automata (n1).

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Non-Uniform Cellular Automata

• Definition 2 Given a trajectory Z, an event
  attributed to automaton j is a change event iff
  Zpj ? Zqj where p?q, 1p,qm and 1jn.

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Non-Uniform Cellular Automata

• Design of an efficient low-power TPG
• Searching for NUCA topology with
• minimal interactions among
• minimal value switching automaton units
• while generating the given sequence

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The Algorithm

• Model
• Dynamic power consumption due to switching
  activities. (more dominant)
• Weighted Switching Activity (WSA) of units
• (Output switching and fan-out values)
• Unit switching cost 0.5CiVDD2
• where Ci equivalent output capacitance
• VDD power supply voltage

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The Algorithm

• Model (cntd.)

Assumed constant
WSA
where C0 minimum size parasitic capacitance
of the circuit, Sik 1 if applying kth
vector causes switching for unit i,
0 otherwise. Fi fan-out of unit i.
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The Algorithm

• Figuring out NUCA search space
• of different interaction topologies
• of different automaton definitions for i
• where d of different state values
• k of units feeding input to the unit i.

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The Algorithm

• Minimum Set Covering (MSC) Problem
• Idea An occurence of a change event can be
  explained by state value differences at previous
  steps (i.e. steps (p-1) and (q-1)). (Memoryless)

SUBJECT TO
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• Input Two-dimensional activity matrix (Zmxn),
  of rows of Z (m), of columns of Z (n).
• Output A set covering problem whose solution
  gives minimal power consuming NUCA definition.
• CONVERSION (matrix Z, int m, int n)
• /Calculate the switching activity coefficients
  (aj)/
• for j1 to n do
• aj0
• for i2 to m do
• if Z(i-1)j ? Zij then aj aj1
• /Construct the objective function string /
• /Construct the constraint set string P/
• P
• for each automaton Gj
• for each (Zpj, Zqj) pair do
• set current constraint string T to
  empty
• if is a change event then
• for each system component
  Gs do
• if Z(p-1)s ? Z(q-1)s then
  append variable Ejs to the current constraint T

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The Algorithm
E24
E23

• Time complexity ?(m2n2)
• Example
• mn5, S0,1
• For generates
• E23E24 1

2
3
4
3
4
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The Algorithm
Switching count of the 1st column
Switching count of the 5th column
SUBJECT TO
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The Algorithm

• Fan-out for the jth unit
• WSA a1F1a2F2a3F3a4F4a5F5
• 34 30 20 13 21
  17

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Experimental Results

• Implementation 1-bit memory combinational
  circuit.

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Experimental Results

• Environment
• Data ISCAS-85 benchmark.
• Test Vector Sequence ATPG tool (CADENCE).
• Area Cost Calc. Synplify Pro FPGA logic
  synthesis tool.
• Target device Altera Stratix II FPGA.
• Programming Language C
• Optimization Package GAMS-Cplex
• HW Platform Intel P4 2.00 GHz.

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Experimental Results

• Nonlinear Hybrid Cellular Automata (NHCA)
• NUCA with fixed fan-infan-out3
• NHCA
• compact and regular design. (Adv.)
• increased test-length switching (Disadv.)

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Experimental Results
Idea Relax wiring topology to prevent potential
increase in test length switching Metric AST
(Area cost)(Switching activity cost)(Test
length) Ravikumar et.al., 1998
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Experimental Results
Results taken from 8.
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Experimental Results
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Conclusion

• Inverse Problem.
• Minimum Set Covering (NP-Complete!!!).
• NUCA approach.
• Future Improvement
• Parallel implementation of conversion algorithm
  for larger CUT sizes.