Switched Capacitor Filters

1
Switched CapacitorFilters
2
Plan

• Lecture1
• Integration Techniques
• Switched capacitor theory
• Parasitic effects in switched capacitor
  integrators
• Lecture2
• Switched capacitor noise
• Continuous time domain to sampled domain mapping
• Synthesis methods

3
Pole Requirements for stable systems
? Laplace
Transform F(s) ?f(t) est dt

0 From Inverse Laplace Transform all
poles, si ? i jwi of form 1/(s- ? i) , 1/((s
? i) 2bi 2),etc contain factor e ? iT ? ? for
? i gt0
? Z-Transform F(z) ?f(nT)
z -n where z esT
n0 From Inverse
Z-Transform all poles, Zi ai jbi of form
1/(Z-aT) , 1/(Z aT) 2, contain factor anT
Zi n in the transient response ? ? for
Zi gt1
S-Plane
Z-Plane
jb
jw
a
?
For a stable continuous-time system All poles, si
must be in LHP (? i lt 0) Transfer Function
cannot have poles with positive real parts
For a stable sampled system All poles, Zi must
obey Zi lt 1
Objective Map a Continuous-Time (C.T.) domain
(analog) filter transfer function(T.F.), Ha(Sa)
to a Discrete-Time (D.T) domain transfer
function, H(z) by replacing Sa by some function
Sa f(z) Ha(Sa) ? H(z)
with Sa f(z) Question What
are requirements of f(z) to be a good mapping?
4
Requirements for good mapping function f(z)

• Ha(Sa) ? H(z)
• with Sa f(z)
• e.g., Continuous Time Integrator
• Ha(sa) 1/sRC
• Requirements for f(z)
• f(z) is a rational function of z,
  i.e.,a division of two
  polynomial functions
• For s jw, Z1 must be true
• For Re(s) lt 0, Zlt1 must be true

5
Integration Techniques1 (Forward Euler Example)
For a C.T.filter with T.F. Ha(Sa), its response
can be determined from its state equations, a
system of 1st order equations which describe it.
Where xi are the state variables of
the filter gi (t) are linear functions of xi (t)
and the input signal And we assume xi (t) 0
for t lt 0
Eq.1
Eq.2
Now derive the state equations for sampled data
systems Integrating Eq.1 over the nth sampling
period
gi(t)
Forward Euler
nT-T
nT
Now Eq.1 has been transformed into difference
form. Numerical Integration can be used to
evaluate this integral e.g., for the Forward
Euler approximation
6
Integration Techniques2

• nT nT
• ? gi(t)dt ? dxi(t)/dt.dt
  xi(nT) - xi(nT-T)
• nT-T nT-T
• f(z). Xi(z) Gi(z) for some function f(z)

In the same way, different numerical Integration
techniques will give different approximations of
?gi(t)dt and each will yield a different
function f(Z) for transforming from
Continuous-time to Discrete-Time domains.
Integration Technique
xi(nT) - xi(nT-T) Xi(z) z 1
Xi(z) ? Solve for f(z) Gi(z)/Xi(z)
Tgi(nT-T)
T.z 1 .Gi(z) Tgi(nT)
T.Gi(z) (T/2)(gi(nT-T)
gi(nT)) (T/2)(z 1 .Gi(z)
Gi(z)) (Not used because unstable in Z-domain)
gi(t)
a) Forward Euler
nT-T
nT
b) Backward Euler
nT-T
nT
c) Trapezoidal/ Bilinear
nT-T
nT
d) Mid-point
nT-T
nT
7
Integration Techniques3

• Check Mapping properties of f(z) vs Requirements
• e.g., For Forward Euler Mapping
• F(Z) is a Rational Function of Z? Yes.
• Let sa j?a gt j?a (Z-1)/T
• gt z j?a T 1
• But z 1 only at ?a 0
• z 1 at ?a T ltlt 1, I.e., when fs
  1/T gtgt ?a

Z-Plane
jb
a
1
Image of j? axis
H(j ?a )
From how F(Z) functions map poles and zeros from
C.T. to D.T. domains we can see
Continuous-Time Filter
Dominant poles (I.e., closest to j? axis in
s-plane) move towards Z1. (To see this let
?a?0) gt Results in peaking in passband
H(ejwT)
Sampled-Time Filter (Forward Euler)
In Forward Euler Zeros on jw axis are not mapped
onto Z1. So no zeros in Discrete-Time
T.F. gt Deteriorated stopband response
In Backward Euler, dominant poles move away from
Z1 gt Results in rounding in passband
H(ejwT)
Sampled-Time Filter (Backward Euler)
In Backward Euler, Zeros on jw axis not mapped
to Z1 gt Deteriorated stopband response
8
Switched Capacitor Theory

• Resistor equivalent switched capacitor.
• Interest of switched capacitors in IC.
• Basic structures of switched capacitor
  integrators.
• Comparison with continuous time integrator.

9
Principle(Parallel mode)
R
10
Principle(Serial mode)
R
VB
VA
Tc
11
Interest of switched capacitors

• Pole accuracy
• Tolerance on integrated resistor (sR) 20 to 30
• Tolerance on integrated capacitor (sC) 10 to 20
• ?Accuracy on RC poles around 50
• (Or more likely sRC (sR2sC2)0.5 0.36 )
• Tolerance on integrated capacitor matching 0.1
• Tolerance on clock frequency few ppm
• Accuracy on SC poles better than 1
• Components size
• High resistance value PREVIOUSLY BIG RESISTOR
• ? SMALL (Switched) CAPACITOR

12
Continuous Time Integrator
4/Continuous Time Integrator
Transfer function
13
Switched Capacitor Integration Techniques
We will establish on the following pages
Correspondance Table Summary Parallel
Switched-Capacitor Integrator ?
Forward Euler Mapping Serial
Switched-Capacitor Integrator ?
Backward Euler Mapping Serial/Parallel
Switched-Capacitor Integrator ? Bilinear Mapping

14
Switched Capacitor Integrator
1/ Parallel Integrator
Sampling Instant
VIN
X
a) Calculate Transfer Function
b) Relate S.D. T.F. to Integration model
This is equivalent to Forward Euler integration
15
Switched Capacitor Integrator
2/ Serial Integrator
Sampling Instant
CI
VIN

-
CU
X
-

VIN
VOUT
a) Calculate Transfer Function
b) Relate C.T. T.F. to Integration model
Equivalent to Backward Euler Integration
16
Switched Capacitor Integrator
3/ Parallel/Serial Integrator
Sampling Instant
VIN
VIN
X
b) Relate C.T. T.F. to Integration model
a) Calculate Transfer Function
2

-
Equivalent to Bilinear Integration
Notice For same RC pole Cu1Cu2Cu/2 of previous
serial or parallel integrators
17
Comparison of parallel and C.T. Integrators
Sample Domain Frequency,w (normalised to w0)
18
Comparison of serial and C.T. Integrators
19
Comparison with parallel/serial integrator
20
Parasitic effects in SC integrators

• Clock overlap
• Parasitic capacitors
• Switch resistance
• Clock feed through
• Charge injection
• Mismatch

21
Need of non overlapping clocks
CI
VIN
VOUT
VOUT
CI
VOUT
22
Non overlapping clocks generator
D1
CK
D1
CK1P
CK1N
CK
CK1P
D2
CK2P
CK1N
CK2N
D2
D1
CK2N
D2
CK2P
23
Parasitic Capacitors (Parallel Integrator)
X
THIS TYPE OF INTEGRATOR IS SENSITIVE TO PARASITIC
CAPACITORS ( INTERCONNECT, JUNCTIONS) POLE
ACCURACY IS NO LONGER TRUE
24
Structure insensitive to parasitic capacitor
(Equivalent Parallel Integrator)
X
VIN
VOUT
NON-INVERTING INTEGRATOR SAME TRANSFER FUNCTION
AS PARALLEL INTEGRATOR EXCEPT THE SIGN POLE
ACCURACY IS RECOVERED
25
Structure insensitive to parasitic capacitor
(Equivalent Serial Integrator)
X
VIN
VOUT
INVERTING INTEGRATOR SAME TRANSFER FUNCTION AS
SERIAL INTEGRATOR POLE ACCURACY IS RECOVERED
26
Switch resistance
After charging C for one (non-overlap) clock
phase
VIN
Ts
i.e., RON.C pole frequency must be more than
twice the sampling frequency for capacitor
charging error of lt0.1
27
Clock Feed-Through
SWITCH ON
SWITCH OFF
TRANSITION ON -gtOFF
VC
VIN
VG

• CLOCK FEED-THROUGH INDUCES DC OFFSET BUT NO
  NON-LINEARITY
• because no dependency on VIN

ICgs
28
Clock Feed-Throughcompensation methods (1)
VG2
DUMMY SWITCH
ICgd2
SINGLE TYPE OF SWITCH NMOS OR PMOS
TRUE IF
AND
29
Clock Feed-Throughcompensation methods (2)
VC
VGp
VIN
ICgsn
VGp
COMPLEMENTARY SWITCHES NMOS AND PMOS
TRUE IF
AND
30
Charge Injection

• When VgV is applied, P-type acceptor Holes are
  
• repelled from surface
• Negative acceptor atom space charge left in
  depletion layer
• As Vg increases, an inversion layer of electrons
  forms at surface
• This negative charge is redistributed when Vg?0

VgV
N
N
SWITCH ON
Pwell
Vg0
N
SWITCH OFF
Pwell
31
Charge Injection
SWITCH ON
SWITCH OFF
VG
1-?
?
TRANSITION ON -gtOFF
VC
VIN
D
? DEPENDS ON THE IMPEDANCES SEEN AT VIN AND VC
TERMINALS
?CHARGE INJECTION INDUCES NON-LINEARITY because
charge injection has a dependency on VIN
32
Charge Injectioncompensation method
Towards low-impedance input
CHARGE INJECTION
HIZ AT Cu SIDE
CLOCK NON-OVERLAP
SAMPLING
CHARGE INJECTION
Dont care
SAMPLING
RE-DISTRIBUTION
33
Mismatch
5?
25?
5?
C2
C2
25?
5 ?
5?
5?
C1
C1
5 ?
34
Noise in SC integrators

• Low pass filtering
• Sampling
• Aliasing
• Holding

35
SAMPLING HOLD LOW-PASS FILTERED WHITE NOISE
PSD Power Spectral Density
Sampling frequency Fs1
-3dB frequency Fp2
PSD WHITE NOISE
PSD AFTER LPF
PSD AFTER HOLD
PSD AFTER SAMPLING
36
LOW-PASS FILTERED WHITE NOISE
Switch model Resistor in series with Johnson
Noise source
4kTRdf
RON
C
? Total noise power is independent of RON
37
SAMPLING LOW-PASS FILTERED WHITE NOISE
0
-2
-4
-6
Gain(dB)
-8
-10
-12
-14
-3
-2
-1
0
1
2
3
Frequency
PSD AFTER LPF
PSD AFTER SAMPLING
SAMPLING
? As RON decreases, PSDSAMPLED increases
?
38
EFFECT OF UNDERSAMPLINGALIASING
Fp2 Fs10
Fp2 Fs5
2?
Fp2 Fs1
Fp2 Fs2
0
39
HOLDING SAMPLED LOW-PASS FILTERED WHITE NOISE
PSD AFTER SAMPLING
PSD AFTER HOLD
EQUIVALENT BANDWIDTH
Double sided PSD
Under-sampling factor
Hold function
calculated in Mathematica
40
Switching Noise Conclusions

• The total noise in the baseband (-fc/2 lt f lt fc
  /2 )
• due to replicas is kT/C
• Aliasing due to sampling concentrates the full
  noise-
• power of RON into the baseband
• It is futile to reduce RON below Tsettling
  requirements
• since, while direct thermal-noise PSD
  decreases,
• aliasing increases, and the two effects
  cancel
• Increasing C and fc reduces both direct and
  aliased
• thermal-noise PSDs
• C since reduces total noise power kT/C
• fc since baseband is wider while total noise
  kT/C is constant

41
Idea Pre-Distortion

• Each of these integration techniques distorts
  the frequency axis, w, in the
• sampled-domain
• Pre-distortion of the continuous-time function
  frequency variable, wa to wap
• with a suitable pre-distortion function,
• and then mapping the resulting pre-distorted
  filter function Ha(Sap) to the
• Z-domain
• will avoid distortion of the original poles and
  zeros in the Z-domain filter.
• ? This will be illustrated in the next example

42
Predistortion of single-type (Forward Euler)
integrator
VOUT2
Overall phase error ? Tc
43
Predistortion of single-type (Forward Euler)
integrator
44
Poles pre-distortion
Predistortion of single-type (Forward Euler)
integrator
CONTINOUS TIME FILTER HAS TO BE SYNTHESIZED USING
POLE PRE-DISTORTION METHOD TO OBTAIN THE DESIRED
FREQUENCY RESPONSE WITH SAMPLED FILTER
45
Method1 Poles pre-distortion
Predistortion of single-type (Forward Euler)
integrator
0.01ltFslt10
Pre-Distorted Pole
Desired Pole -1,1
Distorted Pole
46
Predistortion of single-type (Backward Euler)
integrator
47
Predistortion of single-type (Backward Euler)
integrator
48
Predistortion of both-type (Bilinear) integrator
CI
?1
?2
VOUT1
VIN
VOUT2
Overall phase error 0
49
Predistortion of both-type (Bilinear) integrator
50
Predistortion of both-type (Bilinear) integrator
Example Bilinear Transform
Ha(Sa) ? H(z) with Sa f(z)
Notation wa continuous-time frequency
variable wap pre-distorted continuous-time
frequency variable w discrete-time domain
frequency variable
i.e., w does not map onto wa and so w-axis in z-
domain is warped (i.e., bent or compressed)
Instead pre-warp (or pre-distort) wa ? wap and
use wap instead in f(z)
i.e., Pre-warping now maps w ? wa So poles,
zeros will now be mapped correctly
51
SC Filters synthesis methods

• Synthesis from LC ladder network
• Mapping method1
• Mapping Method2
• Ladder Filter Design Example
• Synthesis from active RC filters
• Bi-quadratic switched capacitor example
• Use of bilinear transform
• Exact transfer function

52
SC Filters synthesis methods

• Synthesis from LC ladder network
• Mapping method1
• Mapping Method2
• Ladder Filter Design Example
• Synthesis from active RC filters
• Bi-quadratic switched capacitor example
• Use of bilinear transform
• Exact transfer function

53
Synthesis from RLC ladder(1)
Get nodal equations using Kirchoffs Laws 1)
?I0 at node x 2) ?V0 around loop y and solve
54
Synthesis from RLC ladder(2)
I2
V0
V1
V3
V4
V6
VOUT
VIN
V2
V5
Vp2 I2.R
Vp4 I4.R
Vp5 I5.R
Vp0 I0.R
Vp1 I1.R
Vp3 I3.R
Vp6 I6.R
55
Synthesis from RLC ladder(3)
56
SC Filters synthesis methods

• Synthesis from LC ladder network
• Mapping method1
• Mapping Method2
• Ladder Filter Design Example
• Synthesis from active RC filters
• Bi-quadratic switched capacitor example
• Use of bilinear transform
• Exact transfer function

57
Ladder Filter Design Example (1)
Starting point LCR prototype Ladder filter
configuration
L2
Rs
V1
V3
I2
C1
RL
C3
Vin
Vout
Get nodal equations using Kirchoffs Laws 1)
?I0 at node x 2) ?V0 around loop y Subsequent
equations alternate from V to I
58
Ladder Filter Design Example (2)
Arrange equations schematically. Each -1/s gain
stage will become an integrator
59
Ladder Filter Design Example (3)
Replace each -1/s gain stage by its continuous
time equivalent circuit
60
Ladder Filter Design Example (4)
Replace Rs by switched capacitors
61
SC Filters synthesis methods

• Synthesis from LC ladder network
• Mapping method1
• Mapping Method2
• Ladder Filter Design Example
• Synthesis from active RC filters
• Bi-quadratic switched capacitor example
• Use of bilinear transform
• Exact transfer function

62
SC Building Blocks
Z-domain Transfer Function
Non-Inverting S/C ()
VN
VIN
VN-1
VIN
?Q
Requiv T/C 1/(f.C) For positive Rs
F1
C
F2
VN
VOUT
VN-1
VN
Inverting S/C
VIN
VN-1
?Q
VIN
F1
Requiv T/C 1/(f.C) For negative Rs
-CZ-1
F2
VN-1
VOUT
VN-2
Unswitched C
?Q
VIN
C(1-Z-1)
VIN
?Q
(-1/C)/(1-Z-1)
() Note
Is an inverting integrator
VOUT
63
Cascade Filter Design Biquad Example (1)
Second-order S/C Biquad
Where (definition) ?0 pole frequency of pole
sp ?p? p
Q Quality factor of H(s)
jw
sp
jwp
As Q increases, sp becomes closer to the
jw-axis gt Get peaking of H(jw) near wo
?
?p
64
Biquad Design Example (2)
65
Biquad Design Example (3)

• Use switch-cap building blocks to replace
• resistors
• Non-inverting for Rgt0, CT/R
• Inverting for Rlt0, CT/R
• Remove all redundant switches

C1T.K0/w0 C2C3 T.w0 C4 T.w0
/Q C1T.K1 C2 K2
66
Biquad Realisation Footnote

• Note that in the Biquad example above we assumed
  wTltlt 1
• It is fairly easy to get the exact transfer
  function (T.F.) of the final circuit above
• by replacing each integrator and branch by
  its z-domain T.F.
• Refer to Z-domain equivalents on Building Blocks
  slide
• Then compare required H(Z) polynomial with
  calculated T.F.
• and choose suitable values for components.
• This will result in a more accurate filter
  realization.
• ? See the following 4 slides
• Limitation For filters with High-Q poles, I.e.,
  close to jw-axis (or to unit circle in Z-domain)
• response becomes sensitive
  to process variations.
• May become impractical,
  non-economical

67
SC Filters synthesis methods

• Synthesis from LC ladder network
• Mapping method1
• Mapping Method2
• Ladder Filter Design Example
• Synthesis from active RC filters
• Bi-quadratic switched capacitor example
• Use of bilinear transform
• Exact transfer function

68
Getting exact transfer function of synthesized
Biquad Switched Capacitor Equivalent
69
Synthesis from RC active filters (3)
Getting exact transfer function of synthesized
Biquad Switched Capacitor Equivalent
CHARGE RE-DISTRIBUTION TABLE
70
Use of bilinear transform
Getting exact transfer function of synthesized
Biquad Switched Capacitor Equivalent
71
Use of bilinear transform
Getting exact transfer function of synthesized
Biquad Switched Capacitor Equivalent
72
Use of bilinear transformpre-distortion
Getting exact transfer function of synthesized
Biquad Switched Capacitor Equivalent
73
Use of bilinear transformCoefficients
identification
Getting exact transfer function of synthesized
Biquad Switched Capacitor Equivalent
74
References

• Analog MOS Integrated Circuits for Signal
  Processing
• by Roubik.Gregorian, Gabor C.Temes
• CMOS Analog Circuit Design
• by Phillip E.Allen, Douglas R.Holberg
• Analysis and Design of Analog Integrated
  Circuits
• by Paul R.Gray, Robert G.Meyer

P.Considine Oct, 2001