CS 140 Lecture 6: Other Types of Gates

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CS 140 Lecture 6 Other Types of Gates

• Professor CK Cheng

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Combinational Logic Other Types of Gates

• Universal Set of Gates
• Other Types of Gates
• XOR
• NAND / NOR
• Block Diagram Transfers

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Universal Set
Universal Set A set of gates such that every
switching function can be implemented with gates
in this set. Ex AND, OR, NOT AND, NOT OR,
NOT
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Universal Set
Universal Set A set of gates such that every
Boolean function can be implemented with gates in
this set. Ex AND, OR, NOT AND, NOT OR can be
implemented with AND NOT gates ab
(ab) OR, NOT AND can be implemented with OR
NOT gates ab (ab) XOR is not
universal XOR, AND is universal
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iClicker

• Is the set AND, OR (but no NOT gate) universal?
• Yes
• No

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NAND, NOR NOR XOR, AND X
1 X1 X1 X if constant 1 is
available.
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Universal Set
Remark Universal set is a powerful concept to
identify the coverage of a set of gates afforded
by a given technology.
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Other Types of Gates
X
Y
1) XOR X Y XY XY
XY
XY

• Commutative X Y Y X
• Associative (X Y) Z X (Y
  Z)
• 1 X X 0 X 0X 0X X
• X X 0, X X 1

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e) if ab 0 then a b a b
Proof If ab 0 then a a (bb) abab
ab b b (a a) ba ba ab ab
ab ab a b f) X XY XY (X
Y) X ?? To answer, we apply Shannons
Expansion.
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Shannons Expansion (for switching functions)
Formula f (x,Y) x f (1, Y) x f (0,
Y) Proof by enumeration If x 1, f (x,Y) f
(1, Y) 1f (1, Y) 1f(0,Y) f (1, Y) If x
0, f(x,Y) f (0, Y) 0f (1, Y) 0f(0,Y)
f(0, Y)
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Back to our problem

• X XY XY (X Y) X ?
• X (XY) (XY) (X Y) X f (X,
  Y)
• If X 1, f (1, Y) 1 Y 0 1 1
  Y
• If X 0, f (0, Y) 0 0 Y Y 0
  0
• Thus, f (X, Y) XY

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XOR gates

• iClicker a(b c) (ab) (ac) ?
• Yes
• No

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2) NAND, NOR gates NAND, NOR gates are not
associative Let a b (ab) (a b) c ? a
(b c)
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3) Block Diagram Transformation a) Reduce
of inputs.
?
?
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b. DeMorgans Law
?
(ab) ab
?
(ab) ab
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c. Sum of Products (Using only NAND gates)
?
?
Sum of Products (Using only NOR gates)
?
?
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d. Product of Sums (NOR gates only)
?
?
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NAND, NOR gates
Remark Two level NAND gates Sum of Products Two
level NOR gates Product of Sums
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Part II. Sequential Networks
Memory / Timesteps
Clock
Flip flops Specification Implementation