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CPRE 583Reconfigurable ComputingLecture 21 Fri

11/12/2010(Synthesis)

Instructor Dr. Phillip Jones (phjones_at_iastate.edu

) Reconfigurable Computing Laboratory Iowa

State University Ames, Iowa, USA

http//class.ee.iastate.edu/cpre583/

Announcements/Reminders

- HW3 finishing up (hope to release this evening)

will be due Fri12/17 midnight. - Two lectures left
- Fri 12/3 Synthesis and Map
- Wed 12/8 Place and Route
- Two class sessions for Project Presentations
- Fri 12/10
- Wed 12/15 (??)
- Take home final given on Wed 12/15 due 12/17 5pm

Initial Project Proposal Slides (5-10 slides)

- Project team list Name, Responsibility (who is

project leader) - Team size 3-4 (5 case-by-case)
- Project idea
- Motivation (why is this interesting, useful)
- What will be the end result
- High-level picture of final product
- High-level Plan
- Break project into mile stones
- Provide initial schedule I would initially

schedule aggressively to have project complete by

Thanksgiving. Issues will pop up to cause the

schedule to slip. - System block diagrams
- High-level algorithms (if any)
- Concerns
- Implementation
- Conceptual
- Research papers related to you project idea

Projects Ideas Relevant conferences

- FPL
- FPT
- FCCM
- FPGA
- DAC
- ICCAD
- Reconfig
- RTSS
- RTAS
- ISCA

- Micro
- Super Computing
- HPCA
- IPDPS

Initial Project Proposal Slides (5-10 slides)

- Project team list Name, Responsibility (who is

project leader) - Project idea
- Motivation (why is this interesting, useful)
- What will be the end result
- High-level picture of final product
- High-level Plan
- Break project into mile stones
- Provide initial schedule I would initially

schedule aggressively to have project complete by

Thanksgiving. Issues will pop up to cause the

schedule to slip. - System block diagrams
- High-level algorithms (if any)
- Concerns
- Implementation
- Conceptual
- Research papers related to you project idea

Weekly Project Updates

- The current state of your project write up
- Even in the early stages of the project you

should be able to write a rough draft of the

Introduction and Motivation section - The current state of your Final Presentation
- Your Initial Project proposal presentation (Due

Fri 10/22). Should make for a starting point for

you Final presentation - What things are work not working
- What roadblocks are you running into

Projects Target Timeline

- Teams Formed and Idea Mon 10/11
- Project idea in Power Point 3-5 slides
- Motivation (why is this interesting, useful)
- What will be the end result
- High-level picture of final product
- Project team list Name, Responsibility
- High-level Plan/Proposal Fri 10/22
- Power Point 5-10 slides
- System block diagrams
- High-level algorithms (if any)
- Concerns
- Implementation
- Conceptual
- Related research papers (if any)

Projects Target Timeline

- Work on projects 10/22 - 12/8
- Weekly update reports
- More information on updates will be given
- Presentations Last Wed/Fri of class
- Present / Demo what is done at this point
- 15-20 minutes (depends on number of projects)
- Final write up and Software/Hardware turned in

Day of final (TBD)

Project Grading Breakdown

- 50 Final Project Demo
- 30 Final Project Report
- 30 of your project report grade will come from

your 5-6 project updates. Fridays midnight - 20 Final Project Presentation

What you should learn

- Intro to synthesis
- Synthesis and Optimization of Digital Circuits
- De micheli, 1994 (chapter 1)

Synthesis (big picture)

Synthesis Optimization Architectural

Logic

State Min

Boolean Function Min

Boolean Relation Min

Scheduling

Sharing

Coloring Covering

Satisfiability

Graph Theory

Boolean Algebra

Views of a design

Behavioral view

Structural view

PC PC 1 Fetch(PC) Decode(INST)

Mult

Add

Architectural level

RAM

control

S1

S2

Logic level

DFF

S3

Levels of Synthesis

- Architectural level
- Translate the Architectural behavioral view of a

design in to a structural (e.g. block level) view - Logic
- Translate the logic behavioral view of a design

into a gate level structural view

Behavioral view

Structural view

PC PC 1 Fetch(PC) Decode(INST)

Mult

Add

Architectural level

RAM

control

S2

S1

Logic level

DFF

S3

Levels of Synthesis

- Architectural level
- Translate the Architectural behavioral view of a

design in to a structural (e.g. block level) view - Logic
- Translate the logic behavioral view of a design

into a gate level structural view

- ID Func. Resources
- Schedule use (control)
- Inter connect (data path)

Behavioral view

Structural view

PC PC 1 Fetch(PC) Decode(INST)

Mult

Add

Architectural level

RAM

control

S2

S1

Logic level

DFF

S3

Levels of Synthesis

- Architectural level
- Translate the Architectural behavioral view of a

design in to a structural (e.g. block level) view - Logic
- Translate the logic behavioral view of a design

into a gate level structural view

Behavioral view

Structural view

PC PC 1 Fetch(PC) Decode(INST)

Mult

Add

Architectural level

RAM

control

S2

S1

Logic level

DFF

S3

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if

ALU

Memory Steering logic

Control Unit

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if

ALU

Memory Steering logic

Control Unit

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

read

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

,

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

S8

,

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step

size clkrise_edge x1 lt x dx u1 lt u

(3 x u dx) (3 y dx) y1 lt y u

dx if( x1 lt a) then ans_done lt 0

else ans_done lt 1 end if x lt x1 u lt

u1 y lt y1

Control Unit

S1

S10

S9

S2

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step

size clkrise_edge x1 lt x dx u1 lt u

(3 x u dx) (3 y dx) y1 lt y u

dx if( x1 lt a) then ans_done lt 0

else ans_done lt 1 end if x lt x1 u lt

u1 y lt y1

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

S1

S10

S9

S2

write

S8

S3

S7

S6

S4

S5

ALU

Control Unit

Memory Steering logic

Example Diffeq Forward Euler method

y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step

size clkrise_edge x1 lt x dx u1 lt u

(3 x u dx) (3 y dx) y1 lt y u

dx if( x1 lt a) then ans_done lt 0

else ans_done lt 1 end if x lt x1 u lt

u1 y lt y1

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if
- x lt x1
- u lt u1
- y lt y1

Control Unit

DFF

DFF

DFF

DFF

ALU

Control Unit

Memory Steering logic

Optimization

- Combinational
- Metrics propagation delay, circuit size
- Sequential
- Cycle time
- Latency
- Circuit size

Optimization

- Combinational
- Metrics propagation delay, circuit size
- Sequential
- Cycle time
- Latency
- Circuit size

Impact of Highlevel Syn on Optimaiztion

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if

ALU

Memory Steering logic

Control Unit

Impact of Highlevel Syn on Optimaiztion

- y 3xy 3y 0, where x(0) 0 y(0) y

y(0) u, for x 0 to a, dx step size - clkrise_edge
- x1 lt x dx
- u1 lt u (3 x u dx) (3 y dx)
- y1 lt y u dx
- if( x1 lt a) then
- ans_done lt 0
- else
- ans_done lt 1
- end if

ALU

Memory Steering logic

Control Unit

ALU

Memory Steering logic

Control Unit

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Sum of products

ABCD ABCD ABCD ABCD ABCD

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

K-map

CD

Sum of products

00

01

10

11

AB

ABCD ABCD ABCD ABCD ABCD

1

1

1

1

00

01

0

0

1

0

0

0

0

0

10

0

0

0

0

11

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

K-map

CD

Sum of products

00

01

10

11

AB

ABCD ABCD ABCD ABCD ABCD

1

1

1

1

00

01

0

0

1

0

0

0

0

0

10

0

0

0

0

11

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

K-map

CD

Sum of products

Sum of products (minimized)

00

01

10

11

AB

ABCD ABCD ABCD ABCD ABCD

1

1

1

1

00

A B ACD

01

0

0

1

0

0

0

0

0

10

0

0

0

0

11

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Multi-level high-level view

ABCD ABCD

A xy xw B xw

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Multi-level high-level view

ABCD ABCD

A xy xw B xw

(xy xw) (xw)CD (xy xw)(xw)CD

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Logic-level Synthesis and Optimization

- Combinational
- Two-level optimization
- Multi-level optimization
- Sequential
- State-based models
- Network models

Introduction to HW3

Introduction to HW3

Introduction to HW3

Next Lecture

- MAP

Notes

- Notes