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CERN%20participation%20to%20EUDET

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Title: CERN%20participation%20to%20EUDET


1
CERN participation to EUDET for TPC electronics
CERN, 31 August 2006
  • Outline
  • Part I Development of the readout electronics
    for the LPTPC
  • Part II RD on the readout electronics for the
    LC TPC

2
PART I Development of the readout electronics for
the LPTPC
3
General requirements and strategy (1/2)
Joachim Mnich (25.10.2005)
  • Readout electronics for the Large Prototype TPC
    (LPTPC)
  • modular with well defined interface for
  • various amplifcation technologies (GEM
    µMegas)
  • different module geometries
  • easy to use and modern DAQ system
  • integrated pre-amps and digitization on TPC end
    flange
  • should be first step towards ILC TPC electronics
  • Two strategies pursued in EUDET
  • new TDC (Rostock)
  • ALTRO-based (Lund, CERN)

4
ALICE TPC Front End Card
Integrated charge amplification, digitization and
signal preprocessing in the TPC end plate
128 channels
5
Readout Control Backplane
Readout and Control Backplane
25 Front End Cards
  • Readout Bus (BW 200 MB /sec)
  • VME-like protocol syncrhonous block transfer
  • Control Bus (BW 3 Mbit / sec)
  • I2C interface interrupt feature
  • point-to-point lines for remote power control of
    FECs

6
Readout Control Unit 3/3
ALICE TPC RCU (requires DDL PCI RORC)
Detector Data Link
Ethernet interface TTC Interface
DCS CARD
Power Regulators
7
USB to FEC Interface Card (U2F)
The U2F Card can read up to 16 FECs (2048
channels)
U2F Card
  • U2F is functionally identical (readout and
    monitoring) to the RCU
  • ALICE Detector Data Link (DDL) and DCS Ethernet
    link replaced by USB link

8
SPI Card ALICE TPC FEC
Reading GEM and MICROMEGAS with the ALICE TPC FEC
Signal Polarity Inverter (SPI) Card
9
An example HARP FC GEM R/O SPI FEC U2F
CERN PS, November 2005
10
General requirements and strategy (2/2)
  • In the EUDET Collaboration Meeting at Nikhef (Jan
    06), it was decided
  • For the LPTPC only the ALTRO based solution will
    be pursued
  • 1000 or 2000 channels according to the
    availability of ALTRO chips
  • system components and responsabilities
  • interface between TPC readout plane and FEE
    (Lund)
  • new shaping amplifer chip (CERN)
  • 40-MHz ALTRO (CERN)
  • Front End Card (PASA ALTRO)
  • new design (based on CERN ALICE FEC) (Lund)
  • production and test (Lund)
  • U2F card (CERN)
  • System integration and test (Lund)
  • DAQ (Lund)

11
Status of CERN contribution
  • Participation to the definition of the interface
    between readout plane and FEE
  • several options are being studied and worked
    out in detail (small CERN contr.)
  • New shaping amplifier chip well advanced (see
    second part of this present.)
  • 40-MHz ALTRO chip about 150 chips have to be
    unsoldered from exsisting
  • FECs (obsolete ALICE prototypes). This work
    is planned for Q1 2007.
  • U2F card (CERN) 4 new boards have been produced
    and tested
  • SPI cards 2 new boards have been produced and
    tested
  • 2 complete readout system (SPI FEC U2F
    Labview Software) have been
  • prepared and transferred to Lund (April) and
    Aachen (June)

12
PART II RD on readout electronics for the LC
TPC General Purpose Charge Readout Chip
13
Motivations Specifications 2/2
  • A general purpose charge readout chip
  • number of channels 32 or 64
  • programmable charge amplifier
  • sensitive to a charge in the range 102 -
    107 electrons
  • Input capacitance 0.1pF to 10pF
  • high-speed high-resolution A/D converter
  • sampling rate in the range 40MHz - 160MHz
  • programmable digital filter for noise reduction
    and signal interpolation
  • a signal processor for the extraction and
    compression of the signal information (charge and
    time of occurrence).

14
Charge Readout Chip Block Diagram
32 / 64 Channel
15
Project Milestones
  • Milestone I (Q1 2007) ? Programmable Charge
    Amplifier (prototype)
  • 16 channel charge amplifier anti-aliasing
    filter
  • Milestone II (Q2 2007) ? 10-bit multi-rate ADC
    (prototype)
  • 4-channel 10-bit 40-MHz ADC. The circuit can be
    operated as a 4-channel 40-MHz ADC or
    single-channel 160-MHz ADC
  • Milestone III (Q2 2008) ? Charge Readout Chip
    (prototype)
  • This circuit incorporates 32 (or 64) channels.
  • Milestone IV (Q2 2009) ? Charge Readout Chip
    (final version)

16
Programmable Charge Amplifier
Gerd Trampitsch
Production Engineering Data
INPUTS
  • 12- channel 4th order CSA
  • various architectures (classical folded cascode,
    novel rail-to-rail amplifier)
  • process IBM CMOS 0.13 mm
  • area 3 mm2
  • 1.5 V single supply
  • Package CQFP 144
  • MPR samples (40) Apr 06

single channel
OUTPUTS
Parameter Requirement Simulation MPR Samples
Noise lt 500e 300e (10pF) 270e (10pF)
Conversion gain 10mV / fC 10mV / fC 9.5mV / fC
Peaking time (standard) 100ns 100ns 100ns
Non linearity lt 1 lt 0.35 0.4
Crosstalk lt0.3 0.4 lt 0.3
Gain dispersion gt 2000 3300 4600
Power consumption lt 20mW 10mW / ch 10mW / ch (30pF cl)
17
Programmable Charge Amplifier
  • The CQFP 144 package has the same pin-count and
    similar pinout as the ALICE TPC PASA
  • In the near future
  • the new chip will
  • be tested on a
  • ALICE TPC FEC
  • Next Step
  • Milestone I (Q4 2006) ? Programmable Charge
    Amplifier (prototype)
  • 16 channel charge amplifier anti-aliasing
    filter
  • Programmable peaking time (50ns 500ns) and gain
  • Submission (?? To be discussed with Sandro)

18
Multi-Channel Time-Interleaved A/D Converter
Upgrade of ALTRO ADC
A/D
A/D
A/D
A/D
A/D
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