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Memory Addressing

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Memory Addressing Byte ( 8 bits) smallest addressable unit in memory Bytes: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 – PowerPoint PPT presentation

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Title: Memory Addressing


1
Memory Addressing
  • Byte ( 8 bits) smallest addressable unit in
    memory
  • Bytes 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
    17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
  • Halfword 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28
    30 32 (16 bits)
  • 16 bits on Halfword boundary
    (lsb of address 0)
  • Words 0 4 8 12 16 20 24 28 32
  • 32 bits on Word boundary (ls 2
    bits of address 0)
  • Doublewords 0 8 16 24 32
  • 64 bits on Doubleword boundary
    (ls 3 bits of address 0)
  • Quadwords 0 16 32
  • 128 Quadword
    4
  • Octowords 0 32
  • 256 Octoword
    5

2
Memory Addressing
  • Virtual Address- created by Processor... The
    logical address is an address in the address
    space of the current process
  • Real Address
  • Created by the Memory Translation
    mechanism..Virtual to real
  • A real address identifies a location in real
    storage. When a real address is used for an
    access to main storage, it is converted, by means
    of prefixing, to an absolute address. (usually
    associated with an LPAR)
  • Absolute Address
  • An absolute address is the address assigned
    to a main-storage location. Multiple LPARS (each
    with a real address space) have blocks
  • In the Absolute address space. In an SMP
    configuration, each Processor's real page zero
    has a different absolute address
  • See fig Mem 1

3
Virtual Memory
  • Virtual Address
  • A virtual address identifies a location in
    virtual storage.
  • When used for an access main storage, it is
    translated to either
  • (a) to a real address, which is then
    converted by prefixing to an
  • absolute address, or
  • (b) directly to an absolute address
  • History
  • 360 -gt 24 bit real (original models did not
    have virtual)
  • 370 -gt 24 bit real and 24 bit virtual
    addressing
  • then 31 bit virtual
  • then 26 bit real (page table entry
    size limit)

4
370 Address Translation
  • An Address space defined by a Segment Table
    Designation(STD)
  • STD is loaded into Control Register (CR) 1
  • - see Fig (1.5)
  • Break virtual address into Seg, Page and offset
    in page
  • Control Register 1 points to Segment table..
  • Seg selects entry in Seg table-
  • it refers to a Page Table
  • Page selects entry in Page Table
  • Page table entry contains real page

5
Dual Address Space Capability
  • - Two address spaces defines by CR1 and CR 7
  • CR1 is primary, CR7 is secondary
  • - Designed to allow to operate on 2 address
    spaces and
  • Pass control between address spaces
  • - Bit in PSW controls the address space mode
  • Instructions are in the Primary space
  • Operands are in Primary or Secondary space
    (Bit in PSW)
  • - Special Instructions move data between
    address spaces,change bit in PSW, and transfer
    control between address spaces
  • - Address spaces identified by an Address Space
    Number (ASN)

6
The Program Status Word (PSW)
  • -Contains PC plus lots of additional Information
  • IO interrupt Enable
  • Protect Key
  • Condition Code
  • User or Kernel Mode
  • Address Translation
  • Interrupt Information when interrupted
  • -Originally 64 bits long, System z expands to 128
  • See fig 1.7

7
Memory Addressing Feature Evolution
  • Dual address space (DAS, 1981)
  • ? Added secondary address space (designated by
    CR7)
  • - CR1 now designates primary address space
  • - instructions to switch between addressing
    modes
  • - Added instructions to move between
    address spaces
  • ? Added PSW address-space-control (ASC, bit 16)
  • - 0 primary space, 1 secondary space
  • 370 / Extended Architecture (XA, 1984)
  • ? Added basic-addressing-mode (B) control
    (PSW.32)
  • ? Allows switching between 24- and 31-bit
    addressing modes

8
Memory Addressing Feature Evolution(2)
  • ??Advanced-space facility (ASF, 1989)
  • ?Added home address space (CR13)
  • ?Added access-register translation
  • ?Extended PSW address-space control (bits 16-17)
  • 00 primary, 01 AR, 10 secondary,
    11 home
  • ?Added linkage stack
  • ?Added numerous instructions for linkage-stack
  • manipulation
  • ??z/Architecture (2000)
  • ? Added extended-addressing mode (E) control
    (PSW.31)
  • ? Allows switching between 24/31-bit modes and
    64-bit mode

9
Memory Addressing Feature Evolution(3)
  • ??Advanced-space facility (ASF, 1989)
  • -Access Registers (AR)
  • AR-specified virtual address- a virtual
    address to be translated by means of an
    access-register-specified address-space-
  • Logical addresses are treated as
    AR-specified addresses when in the
    access-register mode.
  • -Home Virtual Address
  • Home virtual address- a virtual address to be
    translated by means of the home address-space.
  • Logical addresses and instruction addresses
    are treated as home virtual addresses when in the
    home-space mode.

10
Memory Addressing Feature Evolution(4)
  • ??Advanced-space facility (ASF, 1989)
  • The home address space represents the initial
    address space
  • - the space where the control blocks exist,
    and,
  • - if other address spaces are called, the
    space that gets the blame
  • (i.e., terminated) should the task
    encounter an unrecoverable error.
  • ASF also introduced a linkage stack.
  • -This is a push-down stack
  • - used by authorized and unauthorized
    programs
  • - avoids the need for classic saving of
    registers

11
Memory Addressing Feature Evolution(5)
  • ??Advanced-space facility (ASF, 1989)
  • In 2000, z/Architecture added 64-bit addressing
    resulting in the addition of the
    extended-addressing-mode control in the PSW.
  • Some Architecture info
  • PSW Access key (4 bits), problem/supervisor-sta
    te (1 bit), address-space control (2 bits), and
    addressing mode control (2 bits)
  • CR1 Primary address-space-control element
    (ASCE)
  • CR7 Secondary ASCE

12
Memory Addressing Feature Evolution(6)
  • ??Advanced-space facility (ASF, 1989)
  • Example..see Fig 1.8
  • Program Calls
  • A-gtB -gtC -gt D -gtE -gtF -gtB...R returns to F
    then F -gtG
  • Data Movement
  • AS3 ? AS2 then AS3 ? AS1 then AS3 ? AS4

13
Memory Protection
  • Memory Storage keys See fig Mem2
  • -For each 4k real Memory Page
  • a 6 bit entry/page contains
  • Storage Key required to Access
    page
  • A Fetch Protection bit (F)
  • A Change bit (C)
  • A Reference bit (R)
  • -Key Protection Key in PSW must match Key in
    storage array
  • -except Key 0 in PSW go anywhere

14
Memory Protection(2)
  • - In Access Register Mode
  • An Address space can be made Fetch
    only via a bit in the access llist entry
  • - in zArchitecture a Protect bit in Page table
    and Segment Table provide Fetch Protgection
  • - Low Real Addresses are protected to insure
    Interrupt areas.

15
Memory Addressing 24 bit vs 31 bit
  • - Compatibility issues with 24 and 31 bit
    addressing
  • Instructions that clear high order byte
    e.g. Load Address LA
  • 26 bit real requires changes to Page
    Table (2 more bits)
  • BAL passes CC in bits 0 and 1 -----
    replace with BAS
  • BSM Branch and set Addressing mode
  • set old mode in high order bit
  • BASSM Branch and save and Set
    Addressing Mode
  • (Minimize code changes)

16
ESA/370 and ESA/390
  • ESA/370
  • -added 16 (32 bit) Access registers
  • -Added 2 new modes Access register and Home
  • Access reg provide Add. Space (by GPR)
    for operands
  • Home address space uses CR 13 as base
    reg for Segment Table
  • - see fig Mem2.5 for address translation
    changes
  • - see fig Mem 4 for Control register
    assignments

17
Z Architecture
  • Goals
  • Complete 64 Bit
  • 64 bit GPRs and Operands
  • 64 bit Control Regs
  • 64 bit Virtual Addressing
  • 64 bit Real addressing
  • Complete application compatibility
    (including 31 bit to 64 bit
  • inter-operation)
  • Mostly complete compatibility for
    Middle-ware
  • Features easy for programmers to
    exploit

18
Z Architecture
  • Compatibility
  • -Separate operand addressing from
    operand data width
  • e.g. 64 bit data with 31 bit
    addressing
  • 64 bit addressing with 32
    bit data
  • can mix 32 bit data with 64
    bit data
  • Bit in PSW selects mode
  • - Requires more instructions ( about 100)
  • Most instructions are non-Modal i.e.
    addressing mode does not effect
    execution of the instruction
  • - Extra Instructions don't fit in OP
    code, need an extension byte
  • see fig Mem6

19
Z Architecture
  • 64 bit Address Space
  • 24 bit line to handle 360 apps (dusty
    deck)
  • 31 bit bar
  • See fig 3a. For address pace layout
  • 64 Bit address translation... See Fig 3
  • Address Space Control Element (ASCE)
  • Variable number of layers for
    translation (2 - 4)
  • gt Segment Table (ST) gt Page
    Table(PT)
  • gt Region Third
    Level(RTL)gtSTgtPT
    gt Region Second
    Level(RSL)gtRTL gt ST gt PT
  • gt Region First Level
    (RFL)gtRSL gtRTL gt ST gt PT

20
Z Architecture
  • Interrupt Types
  • IO
  • SVC
  • EXT e.g. Timer
  • Machine Check
  • Program Check e.g. page fault
  • Restart e.g. SIGP from
    another process
  • Cause PSW Swap at low memory Address
  • Interrupt code provides additional
    Information e.g. uuu

21
Z Architecture
  • PSW Format
  • See fig Mem7
  • Instruction Types
  • See fig Mem8
  • Low memory Layout
  • See fig Mem9

22
Z Architecture
  • Goals

23
Z Architecture
  • Goals

24
Z Architecture
  • Goals

25
Z Architecture
  • Goals
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