EE%20201C%20Modeling%20of%20VLSI%20Circuits%20and%20Systems%20Chapter%201%20Introduction

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EE 201CModeling of VLSI Circuits and
SystemsChapter 1 Introduction
Instructor Lei He Email LHE_at_ee.ucla.edu
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Instructor Info

• Email LHE_at_ee.ucla.edu
• Phone [phone]
• Office Boelter Hall 6731D
• Office hours
• Tus 2-3pm
• Thur 4-5pm
• or by appointment
• The best way to reach me
• Email with EE201 in subject line

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VLSI Design and Verification Cycle
System Specification
Functional Design and Verification
X(ABCD)(AD)(A(BC)) Y(A(BC))ACDA(BCD))
Logic Design and Verification
Circuit Design and Verification

• Verification techniques
• Formal verification
• Logic/circuit simulation
• Functional and logic emulation

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VLSI Design and Verification Cycle (cont.)
Physical Design and Verification
Fabrication and Testing
Packaging

• Layout verification
• LVS, DRC, ERC
• Timing, SI, PI, DFM (applied to circuit design as
  well)
• Modeling and simulation is a core component for
  design and verification considering
  timing/SI/PI/DFM

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CAD Courses at UCLA

• EE dept.
• EE201A Fundamental to CAD (each fall)
• Basics to all aspects of CAD
• More on combinatorial optimization
• EE201C this course (each Spring)
• Modeling and simulation of timing, signal/power
  integrity, and manufacturability for digital and
  mixed-signal circuits
• Co-development of numerical modeling and
  optimization
• EE209 Better Interface between design and
  manufacturing (taught by Puneet Gupta each
  winter)
• CS dept.
• CS258F Physical design of VLSI circuits
• CS258G Logic synthesis of VLSI circuits
• CS259 High Level Synthesis

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201C Course Outline and Schedule

• Interconnect and timing modeling (3 weeks)
• Interconnect extraction
• Delay modeling and model order reduction
• Project 1 (model order reduction in Matlab)
• On-chip timing and integrity (4 weeks)
• Static timing and noise analysis for logic and
  on-chip interconnects
• Process variation, stochastic timing, power and
  noise analysis
• Stochastic power and thermal integrity
• Project 2 (stochastic modeling in Matlab)
• Beyond-die signal and power integrity (3 weeks)
• Chip-package co-design with signal and power
  integrity
• Noise analysis for high-speed signaling and other
  analog components
• Final project Independent study of selected
  topics
• Plus, in-class or video presentations by students

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Programming Projects

• Project 1 Matlab coding of PRIMA
• model order reduction method
• Majority of program is given
• Project 2 Matlab coding of stochastic model
  selected from
• Max operation for timing
• Leakage power due to processing variation
• Eye open for high-speed signaling
• Again, majority of codes is given

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Student Presentation

• One presentation a week by students
• On-campus program (two students a group)
• Video may be used if there is not enough time
  slots
• Online MS program (one presentation per student
  via video)
• Papers and initial slides draft provided
• Final slides and references uploaded to wiki by
  students

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Final Project

• Independent study of selected topic
• Could be a single student or a team of students
• Topic can be decided anytime, but no later than
  week 8
• One or two seed papers provided
• Develop a report based on literature search or
  other forms of independent study
• Up to 12 page report using ACM style
  http//www.acm.org/sigs/pubs/proceed/template.htm
• Deliver a 30 minute presentation during the
  finals week, like a conference talk (video for
  online program)
• Again, reports, references, and video uploaded to
  wiki

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References for this Course

• Web sites
• http//eda.ee.ucla.edu/EE201C
• http//eda.ee.ucla.edu/EE201A-04Spring/index.html
• Selected papers leading journals and conferences
• Tan and He, Advanced Model Order Reduction
  Techniques for VLSI Designs, Cambridge
  University Press, pp 1-217, 2006
• H. Bakoglu, Circuits, Interconnects, and
  Packaging for VLSI, Addison Wesley

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Related VLSI CAD Conferences

• ACM IEEE Design Automation Conference (DAC)
• http//www.dac.com (San Diego, Young student
  program)
• International Conference on Computer Aided
  Design(ICCAD)
• Design, Automation and Test in Europe (DATE)
• Asia and South Pacific Design Automation
  Conference (ASP-DAC)
• International symposium on physical design
  (ISPD)
• International symposium on low power electronics
  and design
• International symposium on field programmable
  gate array
• IEEE International Symposium on Circuits and
  Systems (ISCAS)

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Related VLSI CAD Journals

• IEEE Transactions on CAD of Circuits and systems
  (TCAD)
• IEEE Trans. on VLSI Systems (TVLSI)
• ACM Trans. on Design Automation of Electronic
  Systems (TODAES)
• IEEE Transactions on Circuits and Systems (TCAS)
• IEEE Trans. on Computer

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Grading Policy

• Two Matlab Projects 50
• Course presentation 10
• Final project 40
• A ? score gt 85

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Who should take this course

• For students who are motivated to
• Learn SI, power/thermal, DFM for advanced designs
• Understand CAD better
• Become a CAD professional