MEASURE DC CURVES OF BJT

1
Automation Of BJT PNP Silicon versus
Simulation William Berry, Alex Chee, Chris Soh,
Dalton Young Industry Advisor Mr. Bob
Peddenpohl Faculty Advisor Dr. Joseph Elias

Abstract
Technical Description
During semiconductor design, it is
necessary to compare data from physical testing
of a device to simulation data to validate
simulation SPICE models for future designs.
Historically, the BJT versus silicon
measurement comparisons at Cypress Semiconductor
have been done either manually, with all running
simulations, formatting data, and plotting data
performed by an engineer or autonomously, with
non-native simulation tools which are used
specifically to avoid the manual process.
This project aims to automate the process of
formatting the measured data file from an HP 4156
Semiconductor Parametric Analyzer, performing the
simulations across Cypress process models of a
device using Mentors Eldo SPICE circuit
simulator, formatting and plotting the output
data from simulations alongside the original
measured data, and arranging the plots and data
in an intuitive format for Cypress design
engineers (an existing Cypress format).
New Method
vs.
Old Method
MEASURE DC CURVES OF BJT
MEASURE DC CURVES OF BJT
EXTRACT SPICE MODEL
EXTRACT SPICE MODEL
Objective
GET BIAS CONDITIONS FOR SIMS FROM MEAS.
The objective of this project is to
save money and increase productivity for Cypress
Semiconductor. On average, Cypress creates BJT
models once a quarter, and this task takes an
engineer 1 day, with a cost of approximately 1K.
Bigger savings to Cypress, however, come through
quality assurance of the SPICE model. In the most
extreme case, an inaccurate SPICE model could
result in a new all-layer tapeout that would cost
Cypress approximately 500K for a new mask set.
REPEAT 150 TIMES (PROCESS, CURVES, TEMPERATURE)
SIMULATE ELDO MODEL
RUN PROGRAM
A detailed view of the process, in phases
LOAD SIM MEAS INTO EXCEL
The actual process consists of four
phases to get from start to finish. The phases
were created in parallel, but are made to run
end-to-end, with each one processing or
manipulating the data generated by the previous
phase. As seen above phase one of the process
consists of parsing BSIMPRO measured data files
(from HP4156) and creating metafiles (data files
in memory) in the metafile handler for each plot
to be made. Bias conditions and other
information are also extracted in phase one.
Phase two consists of creating the circuit files
for each type of plot to simulate and running the
actual Eldo simulations for all the specified
process models (specified in the user control
file) using the load-balancer, as well as
collecting the data post-simulation. Phase three
consists of plotting all the data into .png files
using gnuplot and generating .csv data files
corresponding to the plots. Phase four consists
of generating the actual HTML webpage and linking
to the data (again, in a familiar format for
Cypress design engineers).
QA MODEL
QA MODEL
High Level Design
PUBLISH MODEL RESULTS ON WEB
PUBLISH MODEL RESULTS ON WEB
(ABOVE) A comparison of the old and new methods.
Note especially the red boxes, which mark
particularly time-consuming or tedious processes
that are eliminated by this automation.
Conclusion
The program has been completed, and has
been used for the Cypress Semiconductor 150nm
programmable technology. Of the original
deliverables specified, all will be delivered
before the end of the semester, and only the user
document has taken extra time. The program will
meet all specifications provided by Cypress, and
should be extensible for future use.
Future Work
Due to its modular construction, there
is already discussion of modifying the existing
code to process npn-type devices, as well as
handle new plot-types and input file formats.
A high-level view of the automation process
Acknowledgement
(ABOVE) The Final Results A Beta-Ic (Gain) Plot,
an Ib,Ic-Vbe (Gummel) Plot, and an Ic-Vce
(Characteristic) Plot, as generated by the
program. (BELOW) The HP4156 Semiconductor
Parametric Analyzer, in use.
The new process is started by initial
input from the HP4156 Semiconductor Parametric
Analyzer. The HP4156 generates data files of
parametric sweeps from a silicon-based BJT, for
which Cypress develops SPICE models. This HP4156
data file is then read and split into the
different plot types which were taken on the
analyzer, and each of the measured data sets is
simulated using Mentors Eldo circuit simulation
tool. Simulations are performed for different
process models developed by Cypress for the
different plot types using a load-balancing tool
across a cluster, and the resulting data is then
formatted and plotted using the gnuplot plotting
program. The final plots and their data are then
arranged into an HTML page for design engineers
to use and present. The program was
developed to be very modular, as seen in the
communication between phases above. All data is
passed through the central data-handling
mechanism, making the addition of new processes
or methods simple. Inside that mechanism, data
is separated on a per-plot basis, making
modification of a single class of plots, or
addition of new plot types and functions, very
simple for future work.
The group would like to acknowledge the
following people for their invaluable assistance
on the project Mr. Bob Peddenpohl, for his
continual guidance and assistance. Dr. Joseph
Elias, for helping to guide the group during the
early development stages. Dr. Regina Hannemann,
for her assistance in keeping the group on-task
and up-to-date with required reports and reviews.

Sponsors
The group would like to thank both Eta Kappa Nu
and Cypress Semiconductor for sponsoring EE 499.