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Lab. 1

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Title: ENEL353 -- Activating the Blackfin GPIO pins Last modified by: smith Created Date: 1/1/1601 12:00:00 AM Document presentation format: On-screen Show (4:3) – PowerPoint PPT presentation

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Title: Lab. 1


1
Lab. 1 GPIO Pin control
  • Using information ENEL353 and ENCM369 text books
    combined with Blackfin DATA manual

2
D Flip flop
  • D input is captured by the first latch of the
    D-Flip-flop on rising edge of a clock signal C,
  • The output of the first latch is captured by a
    second D-flip-flop using an inverted clock signal
  • Thus the input to the D flip flop appears at its
    output on the falling edge of the clock after
    being captured on the rising edge of the clock

3
N flip-flops form a register
  • Putting 32 of this flip-flops together form a
    register
  • If this register is internal to the processor
    core -- system register -- R0, P0, SP, FP,
    CYCLES
  • If external to the core or on another device
    not a system register

4
Memory mapped register
  • The D input values come along the memory data bus
  • Which register is used is controlled by the value
    on the memory data bus
  • The address of the register and the data value
    placed into the register is controlled by
    normal memory instructions issues by the
    processor

5
Building a radio controlled car4 Threads at least
SWITCHES ON FRONT PANELINPUT COMMANDS
LED LIGHTS ON FRONT PANELCONTROLSIGNALS TO RF
TRANS
PROGRAMMABLE FLAGS
LED-CONTROLREGISTER
FIO_FLAG_D Register
EBIU INTERFACE
YOUR PROGRAM RUNNING ON THE BLACKFIN
int ReadSwitches( )
void WriteLED(int )
ProcessDataASM( ) subroutine
D/A
EARPHONES
A/D
VOICE
A/D D/A Interrupt routine
6
Registers used to control PF pins
  • Flag Data register (FIO_FLAG_D)
  • Used to read the PF bits as an input -- (1 or
    0)
  • Need to read pins PF11 to PF8, ignore all other
    pins values

7
Instructions need to access FIO_FLAG_D
  • Set address bus
  • P0.L lo(FIO_FLAG_D) P0,H hi(..
  • Read R0 P0 (X) (32, 16, or 8)?
  • Write P0 R0 (32, 16, or 8)?
  • Select one bit R3 0x0100
    R2 R3 R0
  • Force one bit R2 R3 R0
  • DONT DESTROY VALUE R0 R3 R0

8
Flip flops
  • When they power up in an unknown state could
    be 1 or 0,
  • On power up -- processor designed to put
    flip-flop into known state reset value
  • Whether set to 1 or 0 depends on what flip-flop
    output is connected to
  • Safety reasons sometimes reset to 0 or reset to
    1

9
Flip flops have set and clear capability
  • Make SET 1, and toggle clock and output becomes
    1
  • Make SET 0, and toggle clock and output become
    0

10
  • FLIPFLOP
  • SET
  • FLIPFLOP
  • CLEAR

11
Other GPIO Flip flopsFIO_MASKA_D and
FIO_MASKB_D
  • If bit X 1, tell processor to cause interrupt
    when FIO_FLAG_D bit X is active

12
Interrupt mask registersalso have their own set
/ clear lines
  • FIO_MASKA_C, FIO_MASKB_C
  • FIO_MASKA_S, FIO_MASKB_S

13
Other flip-flop group tell processor whether to
interrupt on input changing or steady. This
register has no meaning if interrupts are not
active
14
Another flipflop group tells processor1)
interrupt on rising / fail edge if EDGE 12)
interrupt on high level or low level if EDGE 0
15
Same flipflop group tells processor1) if no
interrupt then output of flipflop equals the Q
output of flipflop2) If no interrupt then output
of flipflop equals Q output of flipflop
16
Another flip-flop group controls whether the
flip-flop outputs follow the flip-flop inputs or
are high impedance off no useful value
17
  • A key issue with GPIO is whether a pin is to act
    as an input device (bringing things in from the
    outside world into the Blackfin) or as an output
    device (sending things from the Blackfin to the
    outside world)

18
Why do you need to know how to do read (load)
and write (store) on internal registers?
  • Flag Direction register (FIO_DIR)
  • Used to determine if the PF bit is to be used for
    input or output -- WARNING SMOKE POSSIBLE
    ISSUE
  • Need to set pins PF11 to PF8 for input, leave all
    other pins unchanged

19
Making sure that the FIO_DIR is correct for LAB.
1 NOTE may need to change for later
labaoratories
Write the Blackfin assembly language
instruction(s) to load the address of the
internal programmable flag FIO_DIR register into
pointer register P1 then SET the Blackfin PF
lines to act as inputs
include ltdefsBF533.hgt include ltmacros.hgt P1.L lo (FIO_DIR) P1.H hi (FIO_DIR) // Check the requirements need to have all input // Manual says setting a line for input means setting bit values to 0 R0 0 WP1 R0 // This changes All pins ssync // Force Blackfin to do the write (store) NOW not later
Design Error Changes all pins
20
Notice that previous slide WARNS you about a
design error in the code
  • We cant do things this way as it changes all the
    bits in the 16 flip-flops and we only want to
    change 4 values in the flip-flops
  • The same design error is introduced into Lab. 1
    Task 3
  • However, the same design error is found during
    the TDD tests provided to look at the test code
    to see what was being tested

21
These tests DONOT find the design error
22
These tests DO find the design errorand in fact
explain to you why it is likely that your tests
have failed. But you have to read it
23
This test is another indication that you have not
written the code correctly. There must be 12 read
and writes not 6, not 3
24
We have other tests to check that your code is
correct Lab. 1 Task 4
  • People come by and said I have the cable
    correct, but it keeps on telling me I dont
    meaning I did not look at the test to see what
    it was doing so Dr. Smith your Lab. Is wrong

25
Task Initialize the Programmable flag interface
16 I/O lines on the Blackfin
  • Warning could burn out the Blackfin processor
    if done incorrectly
  • You need to set (store a known value to) a number
    of Blackfin internal registers
  • Most important ones
  • FIO_DIR Data DIRection 0 for input
  • FIO_INEN INterface ENable 1 for enabled
  • FIO_FLAG_D Programmable FLAG Data register

26
Setting FIO_DIR to zero for ONLY pins 8, 9, 10
and 11. Other pins unchanged
P1.L lo (FIO_DIR) // include ltdefsBF533.hgt knows FIO_DIR value P1.H hi (FIO_DIR) // R0 0 // DESIGN ERROR changes all pins to 0 // WP1 R0 // This changes All pins // Correct approach use an AND mask operation R1 WP1 // Read the current value R2 0x0F00 (Z) // Prepare the 32-bit mask with bits // 8 to 11 set to 1, other bits 0 R2 R2 // Complement operation // bits 8 to 11 are 0, other bits 1 R3 R1 R2 // R3 bits 0 for bits 8 to 11 // R3 bits FIO_DIR bits otherwise WP1 R3 // Restore FIO DIR with bits 8 to 11 set to 0, ssync // Force Blackfin to do the write (store) NOW not later

27
Registers used to control PF pins
  • Flag Input Enable Register
  • Only activate the pins you want to use (saves
    power in telecommunications situation)
  • Need to activate pins PF11 to PF8 for input,
    leave all other pins unchanged

28
Making sure that the FIO_INEN is correct for
enable of pins 8 to 11
Write the Blackfin assembly language
instruction(s) to load the address of the
internal programmable flag FIO_INEN register
into pointer register P1 then ENABLE the
Blackfin PF lines as inputs
include ltdefsBF533.hgt include ltmacros.hgt P1.L lo (FIO_?????) P1.H hi (FIO_?????) // Check the requirements need to have all input // Manual says setting a line for input means setting bit values to 0 R0 0x0F00 WP1 R0 // This changes All pins 8 to 11 ON (enable), others OFF ssync // Force Blackfin to do the write (store) NOW not later
Design Error Changes all pins
29
Setting FIO_INEN to one for ONLY pins 8, 9, 10
and 11. Other pins unchanged
P1.L lo (FIO_???) // include ltdefsBF533.hgt knows FIO_INEN value P1.H hi (FIO_???) // R0 0x0F00 // DESIGN ERROR changes all pins // WP1 R0 // This changes All pins // Correct approach use an AND mask operation R1 WP1 // Read the current value R2 0x0F00 (Z) // Prepare the 32-bit mask with bits // 8 to 11 set to 1, other bits 0 R3 R1 R2 // R3 bits 1 for bits 8 to 11 // R3 bits FIO_DIR bits otherwise WP1 R3 // Restore FIO INEN with bits 8 to 11 set to 1, ssync // Force Blackfin to do the write (store) NOW not later

30
Task Setting up the programmable flag interface
  • Follow the instructions carefully
  • FIO_DIR direction register write 0s to bits
    8 to 11
  • FIO_INEN input enable register write 1s to
    bits 8, 9, 10, 11
  • Other bits leave unchanged
  • To provide a screen dump of the test result to
    show your code works
  • Use PRT-SCR button and then paste in .doc file.
  • In Lab. 1. the task said -- Check the following
    bit patterns in the manual  pages 14-1 to 14-22
    to make sure that I have got the patterns around
    the correct way.

31
Echoing the switches to the LEDCode in main( )
written in C
int main( ) InitializeGPIOInterface( ) //
Check Lab. 1 for exact name needed InitializeFl
ashLEDInterface( ) // Check Lab. 1 for exact
name needed define SWITCHBITS 0x0F00
// Look in MIPs notes about
//
using a mask and the
// AND
bit-wise operation //
to select desired bits while
(1) // Forever loop
int GPIO_value ReadBlackfinGPIOFlagsASM ( )
int desired_bits GPIO_value
SWITCHBITS int
LED_light_values desired_bits gtgt 8 // Bits
in wrong position
WriteFlashLEDLights(LED_light_values) // to
display on LEDS
32
Building a radio controlled car4 Threads at least
SWITCHES ON FRONT PANELINPUT COMMANDS
LED LIGHTS ON FRONT PANELCONTROLSIGNALS TO RF
TRANS
PROGRAMMABLE FLAGS
LED-CONTROLREGISTER
FIO_FLAG_D Register
EBIU INTERFACE
YOUR PROGRAM RUNNING ON THE BLACKFIN
int ReadSwitches( )
void WriteLED(int )
ProcessDataASM( ) subroutine
D/A
EARPHONES
A/D
VOICE
A/D D/A Interrupt routine
33
LEDs connected to FLASH port
BACKFORWARDRIGHTLEFT??? CONTROL ON Might be
connected to other thingsDONT CHANGEBEHAVIOUR
34
Blackfin Memory Map
  • If P0 is 0x20001000thenR0 P0 readsa
    value fromFLASH BANK 0
  • If R0 is 6 andP0 is 0x1000 thenP0 R0
    placesa value intoSDRAM

35
Set the Bank control register
  • Kit documentation recommends 0x7BB0

7 cyclesnot 15 11 not 15 B 1011 2 cycles 3
cycles
IGNORE 4 cycles
36
Set General Control Register
  • Documentation says set to 0xF for this
    particular FLASH chip

ENABLE ALL
37
WriteFlashLEDASM(long in_value)
  • Read LED data register into processor data
    register (makes a copy)
  • Keep top 2 bits (AND operation) of copy
  • Keep bottom 6 bits of in-par 32-bit in_value
  • OR the two processor data registers
  • Write modified copy back into LED data
    register
  • PROBLEM byte read and writes

38
Laboratory 1 Tasks
  • Download the C Talk-through program.
  • Board check -- Check that you can hear the audio
    output
  • Develop and test the code for initializing the
    Flash Memory and writing to the LEDs
  • Use the provided tests to check your code
  • Routine for initializing the PF GPIO lines
    (programmable flags)
  • Use the provided tests to check your code
  • Develop the ReadProgrammableFlagsASM( ) to read
    the switches
  • Use the provided tests to check your code
  • Develop the Morse code program in C and ASM
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