A multi-channel architecture for high-performance NAND flash-based storage system

1
A multi-channel architecture for high-performance
NAND flash-based storage system

• Jeong-Uk Kang, Jin-Soo Kim, Chanik Park,
• Hyoungjun Park, Joonwon Lee

2
Agenda

• Introduce
• Background
• Multi-channel architecture
• Read Operation
• Write Operation
• Software Architecture
• Stripping
• Interleaving
• Pipelining
• Combined System
• Evaluation
• Conclusion
• Appendix

3
Introduction (1/2)

• Flash Memory? ???? (K9LAG08U0M)
• Write Register ?? ??(twc X 256) program
  ??(tprog)
• ? 2.4MBps
• Read Page ?? ??(tread) Register ?? ??(trc X
  256)
• ? 28.8MBps
• ? 256 2048 Byte (page size) / 8 bit (bus
  width)

? Flash ?? ??? ?? ??? ???? ????.
4
Introduction (2/2)

• ?? ????
• Stripping
• Interleaving
• Pipelining

1-A
Request 1
Request 1
Request 2
Request 3
1-B
Request 2
2
Request 3
Request 1
1
Request 2
Request 3
Request 1
5
Background

• NAND Flash memory
• Total size 128MB (1024 Blocks)
• Block
• Size 64 pages
• Page
• Size 2048B with 64B spare size
• Operation
• Write, Read, Erase
• Features
• Erase before write
• Program/erase cycle 10,0001,000,000
• Read delay 1025us
• Program delay 200 700us
• Erase delay 23ms
• Data transfer 50us (8 or 16 bit bus band width)

6
Multi-channel architecture
Host
DUMBO
CTR
Channel Manager
CPU
Channel Manager
INT
Host interface
NOR FLASH
Channel Manager
SDRAM
Channel Manager
Data 32
Channel Manager
Control Logic
NAND Interface
INT
CTR 32
Buffer 1
DATA 32
Buffer 2
DATA 16
7
Read Operation
Interrupt
Read Data (RD)
HOST
Read Set (RS)
DUMBO
Setup
NAND
Busy
Data Transfer
Read from NAND (RN)
8
Write Operation
Write Data (WD)
Interrupt
Write Confirm (WC)
HOST
Write Set (WS)
DUMBO
NAND Program (NP)
Data transfer
Setup
NAND
BUSY
Write to NAND (WN)
9
Software Architecture
I/O Subsystem (Request Queue Management)
Block Device Driver
KERNEL
Flash Translation Layer (FTL)
Low-level Device Driver (I/O Scheduler, Interrupt
Handler)
File System Data
DUMBO
FTL method Hybrid (???? ?? ??? ??? ?? ?
?) Garbage Collection ??
10
Stripping
RS
RN
RD
without stripping
Channel Manager
RS
RN
RD
with stripping
Channel Manager1
RS
RN
RD
Channel Manager2
WD
WS
WN
WC
NP
without stripping
Channel Manager
WD
WS
WN
WC
NP
with stripping
Channel Manager1
WD
WS
WN
WC
NP
Channel Manager2
11
Interleaving
RS
RN
RD
RS
RN
RD
without interleaving
Channel Manager
RS
RN
RD
with interleaving
Channel Manager1
RS
RN
RD
Channel Manager2
WD
WS
WN
WC
NP
WD
WS
WN
WC
NP
without interleaving
Channel Manager
WD
WS
WN
WC
NP
with interleaving
Channel Manager1
WD
WS
WN
WC
NP
Channel Manager2
12
Pipelining
RS
RN
RD
RS
RN
RD
without pipelining
Channel Manager
RS
RN
RD
with pipelining
Buffer1
Channel Manager
RS
RN
RD
Buffer2
WD
WS
WN
WC
NP
WD
WS
WN
WC
NP
without pipelining
Channel Manager
with pipelining
WD
WS
WN
WC
NP
Buffer1
Channel Manager
WD
WS
WN
WC
NP
Buffer2
13
Combined system
Request 2
Request 4
Request 2
Request 4
Request 1
Request 3
Request 1
Request 3
Interleaving
Request
Striping
Pipelining
Example) Write 2.4 X 8 19.2MBps Read 28.8 X 8
230.4MBps
14
Evaluation (1/3)
WRITE
READ
STRIPPING
INTERLEAVING
PIPELINIG
?
15
Evaluation (2/3)
Putting it all together
Selection is S2I2. 4KB?? ?? ?? ??? ??? ? ??
- Stripping? Sub-request? ??? Page ???? ? -
???? ?? ???? ?? ?? ??? 4KB??? ? ? ?? ??
23.3MBps, 16.0MBps
16
Evaluation (3/3)
Block Device Driver
17
Conclusion

• ?? ?? ?? ? 3.6? ??? ?? ? ? ???.
• Ideal? ??? 80?? ??? ????.
• ?DMA? ?? ??? ? ?? ???.
• Real work-load? ?? ??? ????.

18
Appendix
19
Issues

• ??? ???? ??? ????
• Mapping Algorithm
• ?? ???? ???? ??? ???? ??? ??.
• Hybrid? Mapping??? ????? ?? ??? Sequential Block?
  ???? ????. ? Block mapping?? ??
• Page mapping? ???? ??? ???? Garbage Collection?
  ????? ???.
• Minor issues
• ?? ??? ?? ?? ???
• ???? ??? ???? ??? ??? ???? ??
• FLASH? ????? ??? ??? ?? ? ?? ????? ???? ?? ???
  ???
• ?? ?????? ?? ??? 4KB?? ?? ??? 4KB ??? ???? ????
  ??
• Channel Manager ? ?? Flash? ?? ?? Program? ??
• EXT4? ?? ??? ????? ?? ??? ?? ??? ??
• Kernel? FTL? ??
• ?? ??? FTL? ?? ??? ?? ??
• Mapping ? Garbage Collection?? ??
• A. Ban, Flash file system, United States Patent
  No. 5,404,485, April 1995. ? Garbage Collection?
  ?? ??? ??

20
Plane Parallelism (1/2)
Sector
Copy to Register
Cell program
800ms
93ms 2KB (Page Size) X twc (8bit wired)

• Atomic write? ????? ? (CPU Intensive operation)
• ??? ??? ??? ???

• CPU? ???? ????? ??? ??
• Cell??? ???? ??? ???? ???? ???

? Register Write Speed 35.7MB/S ? Actual Write
Speed 4.3MB/S
21
Plane Parallelism (2/2)
Copy to Register
Copy to Cell
Copy to Register
Copy to Cell
Copy to Register
Copy to Cell
Copy to Register
Copy to Cell
1172ms13.3MB/S
4ch
Flash
13.3 X 4 55.4MB/S
22
References

• K9XXG08UXM Datasheet, Samsung Electronics