Digital System Design 1 - PowerPoint PPT Presentation

Loading...

PPT – Digital System Design 1 PowerPoint presentation | free to download - id: 752cfd-NzljO



Loading


The Adobe Flash plugin is needed to view this content

Get the plugin now

View by Category
About This Presentation
Title:

Digital System Design 1

Description:

Digital System Design 1 Hardware Realizations – PowerPoint PPT presentation

Number of Views:22
Avg rating:3.0/5.0
Slides: 27
Provided by: vkepuska
Learn more at: http://my.fit.edu
Category:

less

Write a Comment
User Comments (0)
Transcript and Presenter's Notes

Title: Digital System Design 1


1
Digital System Design 1
  • Hardware Realizations

2
Introduction
  • The next step in the design process is to
    translate AHPL control sequence into hardware.
  • Another major part of the design process is the
    development of the control unit.
  • This section deals with the hardwired approach to
    control unit.
  • Another approach is to use micro-programmed
    control unit.

3
Starting, Stopping, and Resetting
  • One of the more subtle problems associated with
    the design of control unit is how to get it
    started.
  • Assumed control unit design (1 flip-flop per
    control step) once a single-clock-period level
    has been established at the input to any single
    flip-flop, the desired sequence of levels will
    propagate through the sequence of control
    flip-flops.
  • To start operations at step 1, flip-flop 1 of the
    control unit must be set and all others must be
    reset.
  • This is accomplished by using SET and RESET
    inputs of the flip-flops of control unit
  • Reset line will be connected to the
  • SET input of flip-flop 1, and to the
  • RESET input of all other flip-flops in control
    unit.

4
Starting, Stopping, and Resetting
  • The line reset will be held active as long as the
    reset button is pushed.
  • When the button is released the next clock pulse
    will advance control from step 1 to step 2, and
    the sequence will proceed from there.
  • With this method the system will automatically
    start through its sequence after being reset.

5
Starting, Stopping, and Resetting
  • If it is desirable for the system to remain in a
    reset state while preparations for the new
    operating cycle are carried then this requires
    that step 1 be a wait state. This system will
    remain in the wait state until the start signal
    as shown in Figure 7.1.
  • Implementation of RIC step 1.
  • (start)/(1).
  • Start of main sequence

6
Starting, Stopping, and Resetting
  • Figure 7.2 shows the realization of the first few
    steps of a typical control sequence with both
    start and reset lines.
  • In addition it shows the timing of typical
    reset-start sequence in which it was assumed that
    the system happened to be at the step 3 of the
    sequence at the time of the reset.

7
Reset-start sequence
8
Starting, Stopping, and Resetting
  • When start goes high, control moves to step 2 to
    start the normal sequence. This reset action is
    indicated by the statement
  • CONTROLRESET(1)after the END SEQEUNCE statement
    number in parenthesis indicates control step to
    which the system returns when reset.

9
Starting, Stopping, and Resetting
  • Resetting the system when first turned on.
  • Care must be taken to ensure that the system when
    first turned on does not start with the devices
    at random states.
  • Reset line is driven active as soon as the power
    is first applied and held there for short period
    of time but long enough for the power supplies
    to reach steady state and the clock oscillator to
    stabilize.
  • The reset line then goes inactive automatically
    and the system proceeds with its normal sequence
    or waits for start signal.

10
Starting, Stopping, and Resetting
  • Starting/Resetting the system when in the HALT
    state.
  • The easiest implementation HLT instruction is
    through DEAD END indicating that propagation of
    the control level is simply terminated.
  • Hardware implementation of control steps 70 and
    71 which branch conditionally to the DEAD END at
    step 78 is shown in Figure 7.3.
  • The syntax of DEAD END represents no hardware but
    indicates that nothing is connected to the output
    of corresponding control step.
  • Because DEAD END as described will leave all
    control flip-flops reset, the computer cannot be
    started again without a control reset to enable
    step 1.

11
Hardware Implementation of DEAD END
12
Starting, Stopping, and Resetting
  • If a reset operation affected nothing but the
    control unit previously described behavior would
    have been satisfactory.
  • However, computer reset is used to shut
    everything down and start over when something
    goes wrong.
  • In addition to control unit other sub-systems may
    be reset such as I/O devices, interrupt system,
    status indicators, and even the data registers.
  • HLT is often used to stop a program to give the
    operator a chance to intervene without otherwise
    affecting the status of program.
  • Computer reset is thus undesirable.
  • HALT therefore will be implemented by
  • returning the control to step 1, and
  • Wait for start signal
  • Without otherwise affect the status of the
    computer. This is done at step 71 as shown in
    Fig. 7.4. and step 72 is eliminated.

13
Starting, Stopping, and Resetting
  • Implementation of HLT by return to Step 1

14
Starting, Stopping, and Resetting
  • Timing of the start signal.
  • Modern computers can execute an instruction in a
    few microseconds or even nanoseconds and can
    execute a complete program in a small fraction of
    few a second.
  • If a start signal is derived directly from a
    manual push button, the computer might complete
    the program, execute a HALT, and return to step 1
    before the button has been released, in which
    event it would start again. Such false restarts
    can be prevented by the use of a single-level
    generator.

15
Starting, Stopping, and Resetting
  • single-level generator
  • It can be described by three statements included
    following END SEQUNCE. It requires
  • two memory elements stff and slf, and a
  • CTERM slstart to provide a control connection to
    the implementation of the control sequence
  • END SEQUENCE
  • CONTROLRESET(1)
  • stff ? start
  • slf ? stff
  • slstart stff ? slf.
  • END.

16
Starting, Stopping, and Resetting
  • stff flip-flop accomplishes synchronization of
    start with the clock.
  • Implementation of the partial hardware
    description just given is shown in Fig. 7.5 with
    the corresponding timing diagram.
  • Note that slstart is 1 for only once
    clock-period. It remains 0 until stff goes to 1
    and returns 0 as soon as slf goes to 1.

17
Starting, Stopping, and Resetting
  • Single-start-level generation

18
Starting, Stopping, and Resetting
  • The hardware technique just described will be
    adequate for most digital systems including
    computers.
  • However, there are software aspects to be
    considered in starting and resetting a computer.
  • A control unit can basically do just one think
  • Read an instruction and execute it.
  • Computer cannot be started in any useful sense
    unless it has a program to start executing.
  • To provide this software component of the
    start/reset process, most CPUs include a ROM
    containing a start-up program that will at the
    very minimum allow the user to enter commands
    through keyboard.

19
Starting, Stopping, and Resetting
  • On power up or reset
  • The reset line in addition to
  • Resetting the control unit to the start of the
    fetch sequence
  • Will reset the program counter to the address of
    the first instruction of the start-up program.
  • Start-up program will
  • Establish appropriate starting conditions in the
    system, and
  • Turn control over to the operating system
    software.
  • Note that start-up program is
  • Part of the CPU itself, transparent to the user,
    and
  • It is located in a separate address space
    accessible only during start-up and reset.
  • Because computer has its initialization steps
    built in, there is rarely any need for a separate
    start button. A single reset button is sufficient
    to start the computer over and bring it to a
    condition where it is ready to start accepting
    commands form the user.

20
Multiperiod Operations
  • Assumption in development of control sequence for
    RIC was that all transfer operations could be
    completed in one clock cycle.
  • There are cases in which trasfers or logic
    operations may require more than one clock
    period
  • Memory access.
  • Typically RAM is made in technology that is
    slower than register memory due to cost.
  • Majority of transfers involve registers and the
    clock rate is set to accommodate this fact.
  • Slower transfers will thus requires multiple
    clock cycles.

21
Multiperiod Operations
  • Many different technologies can be used or RAM.
    These technologies differ greatly in signal and
    timing requirements.
  • In terms of control sequence steps required to
    control them majority of memory systems can be
    grouped into three categories
  • Clocked,
  • Slow synchronous, and
  • Asynchronous.

22
Multiperiod Operations
  • Clocked memory
  • Clocked memory is logically equivalent to an
    array of clocked registers.
  • Such memory is fully compatible in speed with the
    control unit.
  • General model of clocked memory is depicted in
    Fig. 3.13

DATA IN
Address Register
DCD(AR)
write
M
Decoder
n bits AR
....
n lines
2n lines
DATA OUT
23
Clocked Memory
  • Clocked Memory has
  • Address lines
  • Input lines
  • Output lines
  • Write enable a single control line which is
    equivalent to the clock line for a register.
  • Clocked Memories are usually small arrays of
    registers that will be located on the same VLSI
    chip as the CPU (e.g., cache).
  • AHPL notation that characterizes memory transfers
    of Clocked memory is given bellow
  • MD ? BUSFN(MDCD(MA)) // memory read
  • MDCD(MA) ? MD // memory write

24
Synchronous and Asynchronous Memory
  • Memory access for this type of memory is more
    than one clocke period.
  • Typical technology for synchronous memory is MOS
    memory.
  • An AHPL description of the internal functioning
    of memory package is not required for modeling
    the device as slow as synchronous memory.
  • However, it is important to interpret the
    input-output specifications of the package in
    terms of the timing and AHPL description of the
    CPU.

25
Synchronous and Asynchronous Memory
  • Let assume a hypothetical case where CPU has a
    clock frequency approximately three times the
    sped of the available memory.
  • Figure 7.6 depicts typical slow synchronous
    memory model organized as 64K 32-bit words.

26
Synchronous and Asynchronous Memory
  • Addresses are provided on a 16-bit ADBUS and data
    are transferred along a 32 bit bi-directional bus
    DBUS. The line, read will be 1 for a memory read
    operation and 0 for memory write. The ADBUS and
    read lines will typically be required to be
    stable for a period of time before enable goes to
    1 initiating the memory operation.

DBUS
SM 64K X 32
DECODER
32
ASSBUS16
read
control
enable
About PowerShow.com