Reconfigurable Computing After a Decade: A New Perspective and Challenges For Hardware-Software Co-Design and Development - PowerPoint PPT Presentation

Loading...

PPT – Reconfigurable Computing After a Decade: A New Perspective and Challenges For Hardware-Software Co-Design and Development PowerPoint presentation | free to download - id: 750a79-ZTMwY



Loading


The Adobe Flash plugin is needed to view this content

Get the plugin now

View by Category
About This Presentation
Title:

Reconfigurable Computing After a Decade: A New Perspective and Challenges For Hardware-Software Co-Design and Development

Description:

Reconfigurable Computing After a Decade: A New Perspective and Challenges For Hardware-Software Co-Design and Development Tirumale K Ramesh, Ph.D. – PowerPoint PPT presentation

Number of Views:23
Avg rating:3.0/5.0
Slides: 21
Provided by: tram157
Learn more at: http://ewh.ieee.org
Category:

less

Write a Comment
User Comments (0)
Transcript and Presenter's Notes

Title: Reconfigurable Computing After a Decade: A New Perspective and Challenges For Hardware-Software Co-Design and Development


1
Reconfigurable Computing After a Decade A New
Perspective and Challenges For Hardware-Software
Co-Design and Development
  • Tirumale K Ramesh, Ph.D.
  • Boeing Associate Technical Fellow
  • Senior Member, IEEE
  • tkramesh_at_ieee.org
  • Northern Virginia Chapter IEEE Computer Society
    Meeting
  • April 14, 2005

2
Outline
  • What is and Why Reconfiguration?
  • Applications
  • Architecture in the past
  • New Architecture Trends
  • Hardware-Software Co-Design and Development
  • Future

3
What is Reconfiguration ?
  • The ability to change the hardware entity as
    warranted by an application. This is an emerging
    field that blurs the traditional boundaries
    between hardware and software.
  • Who will like Reconfigurable Computing ?
  • One who enjoys real-time design and
    applicationsOne with a pioneering spirit to
    learn more on software and knowledgeable about
    hardware (or vice versa)One who likes to produce
    a challenging hardware/software solutions to an
    application

4
Why Reconfigurable Hardware?
  • The one-to-one match of application to a fixed
    architecture is difficult and we cannot achieve
    high throughput
  • Greater functionality can be achieved with a
    reconfigurable logic
  • Lower system cost
  • Evaluate in terms of lifetime system costs to
    determine the savings
  • The ability to provide for high fault tolerance
    in the system
  • Reduced time-to-market
  • Flexible logic and on-the field reprogrammable

5
Applications
  • Defense, Aerospace Automotive Electronics
  • Hybrid Supercomputing for Scientific Applications
  • Hybrid Embedded Computing
  • Hardware Accelerators
  • High-data stream applications-Massive
    Reconfigurable Arrays
  • Image and Signal Processing

6
Types of Reconfiguration
  • Processor Reconfiguration
  • Changing the internal hardware capabilities(Data
    Path- Word size, Pipelining, Communication among
    Multiple Data Path Units, etc.)
  • Communication Reconfiguration
  • A set of communication channels provided in
    run-time for a pair of processors
  • Control Reconfiguration
  • Changes the way in which instructions streams are
    processed on a processor (SIMD, MIMD, MSIMD)

7
Architecture in the past
  • FPGA logic used more as a logic glue and also for
    replacing multiple chips and for reducing the
    chip count
  • Fine-grain logic
  • Not much run-time reconfigurable capability were
    available
  • All designs were done at low level (VHDL)
  • Very limited abstraction at system level
  • Minimal Tools support
  • Used Multiple FPGAs to gain more logic due to
    device density limitations

8
New Architectural Trends
  • Coarse-grain architectures
  • Large IP building blocks
  • Reconfigurable Processor Units(RPU)
  • Custom Interfaces
  • Highly parallel processing elements
  • Morphware Accelerators- Data Stream Engines
  • Coarse-grain data paths units configured as
    high-level parallelism similar to ILP by using
    Configware to program the resources and Flowware
    to program the data streams running through the
    resources.
  • Distributed adaptive boards (FPGA based)
  • Single API for Distributed ACS -Single high level
    host program in C or C with networking code for
    interaction of multiple boards

9
Hardware-Software Co-Design and Development
  • Cooperative design of hardware and software
  • Co design shortens time-to-market due to use of
    flexible software and enhancing performance via
    specific hardware as necessary
  • Reconfigurable hardware adds to flexibility as
    design changes can be made on the field
  • Less expensive than ASIC
  • Co-design is an interdisciplinary activity
  • System level modeling
  • Hardware and software design

10
Hardware-Software Co-Design Flow
System Spec
Cost Analysis Estimation
HW/SW Partitioning
HW Spec
SW Spec
Synthesis
Compile
Simulation and/or Emulation
Design Verification
Design Not Met
11
HW/SW Co-Design of Embedded Reconfigurable Systems
  • Integrating COTS processor, ASIC and Programmable
    Logic on a single platform

System Arch and Performance Profiling
COTS Processor
Reconfigurable Processor
HW/SW Partitioning
On-chip RAM
HW Synthesis
Compiler
FPGA bit streams
12
HW/SW Partitioning in Reconfigurable Systems
  • FPGA Perform Processing Both in Space and Time
  • Space- Refers to Physical Implementation of
    different functionality in vast hardware
    resources (parallel processing)
  • Time-FPGA can be reconfigured at various steps of
    the application algorithm to instantiate
    different architectures at different run
    times(dynamic)
  • Partitioning needs to account for both spatial
    and time domains

13
Key Design Requirements
  • Speed of Reconfiguration
  • Atleast close to the speed of execution
  • Speed, size and density
  • gt100 MHZ, gt8M Logic gates
  • Memory interfaces
  • Support high-data stream- data stream memories
    with fast access time
  • Development Tools
  • Automatic mapping and compiling
  • Integration into low level design synthesis tools

14
System-on-a chip
  • Integrating COTS processor, ASIC and Programmable
    Logic on a single die

Development Tools and Methodologies
ASIC Core
COTS Processor
Simulation/ Emulation Boards
FPGA Core
Mixed-Signal Cores
Silicon Processing
Test and Validate
15
HW/SW Co-Design Languages/Tools
  • Adapting high level languages
  • SpecC- extension of ANSI-C
  • Support embedded systems design, including
    behavioral and structural hierarchy
  • Targeted for system-level design language
    intended for spec and architectural modeling
    though developed for synthesis and verification
    in mind
  • HardwareC-Uniformly incorporates both
    functionality and design constraints
  • SystemC-Uses C class libraries and a simulation
    kernel for creating behavioral and RTL designs

16
HW/SW Co-Design and Development-System
Languages/Tools(Continued)
  • Java based approaches
  • JHDL- Java to RTL Compiler runs Java into
    synthesizable HDL code
  • UML- System level modeling
  • Extend UML to apply them as high level models
    working with other languages
  • UML profile for SystemC- a language that enables
    specify, analyze, design, construct, view SW and
    HW artifacts in a SoC design flow

17
HW/SW Co-Design and Development-System
Languages/Tools (Continued)
  • Extending HDL Languages
  • System Verilog- Blends Verilog, C/C
  • An extension to IEEE 1364-2001 Verilog
  • Supports interfaces that allow module connections
    at a high level of abstraction
  • SuperLog
  • Verilog superset that includes constructs from C
  • Verliog 2001 and SuperLog at two ends of the
    spectrum
  • Utilizes power of C with the simplicity of
    Verilog for a very productive design process

18
Algorithm/Data Flow Tools
  • MATLAB to FPGA Design IP Core Instantiation
  • Xilinx DSP Sys Gen
  • Khorus- Data Flow Tool for Image Processing
  • Ptolomey- Graphical Entry Tool for System Level
    Design

19
Future
  • System-on-a chip (SoC) to gain more logic,
    performance and low cost and power advantages
  • Use of more Modular Block Architectures at the
    device level- Ex Xilinx ASMBL
  • Domain-specific block pre-fabricated with mixture
    of processors, peripherals, and other special
    interfaces to support different application
    domains
  • Use of advanced packaging technology and flexible
    placement of on power and ground
  • More Use of Parallel Processing techniques and
    FPGA architectures for both spatial and time
    domain mapping

20
Future
  • Mix and match of Parameterized and Custom blocks
  • High Level Abstraction Tools with integration to
    low level tools for optimum design process
  • Use of XML for Configuration of processors and to
    specify the targeted hardware devices
  • Allows for adding application-specific
    instructions to a processor
About PowerShow.com