Implementation Of A Testbed For Evaluating Energy Efficiency In Passive Optical Network

1
Implementation Of A Testbed For Evaluating
Energy Efficiency In Passive Optical Network

• Supervisor Submitted by,
• Dr. Luca Valcarenghi Neelakandan Manihatty Bojan

2
Outline

• Introduction
• Scope of the thesis
• State of the art
• Testbed architecture
• Testbed implementation
• Conclusion
• Future scope
• Bibliography

3
Introduction
4
ONU architecture
5
Stratix 4GT FPGA board
6
FPGA architecture
7
Scope of the thesis

• To implement an Energy Efficient ONU (ECONU)
  prototype for EPON in Altera FPGA based on the
  finite state machine (FSM).

8
State of the art
9
Testbed architecture
10
Frame and Packet format
11
VLSI design flow
Design Specification
Behavioral Description
RTL Desctiption (HDL)
FunctionalVerification and Testing
Logic Synthesis
Gate-Level Netlist
LogicalVerification and Testing
Floor PlanningAutomatic Place Route
Physical Layout
Layout Verification
Implementation
12
Birds eye view of the design
13
Negative exponential inter-arrival time
14
Birds eye view of sleep controller module
15
FSM implementation
16
Resource utilization
Device resources summary
Resource utilization of design
17
SignalTap
18
Testbed setup
Simulation Synthesis
Programming the FPGA
.sof (SRAM based object file)
Commands given through System console and Signal
tap
Executes commands and provides the results back
19
Results
There are two main test modes used in the design
Internal Loopback
Local Loopback
20
Sleep time
21
Low power idle time
22
Wake time
23
Analytical evaluation

• Sleep time Ts 2.88µs
• Low power idle time Tlp 39.68µs
• Wake time Tw 4.48µs
• Total sleep time Actual sleep time
  Overhead associated with transitions
• Low power idle time
  Sleep time Wakeup time
• 
  39.68µs 2.88µs
  4.48µs
• 
  47.04µs
• So the overall percentage of the actual sleep
  time in a sleep request
• (Low power idle time / Total sleep
  time)100
• (39.68µs/47.04µs)100
• 84.35
• Similarly the overall percentage of the sleep
  time and the wake time is 6.1 and 9.5
  respectively.

24
Energy efficiency characteristics
Packet size 1500 Bytes
Packet size 1000 Bytes
25
Energy Efficiency characteristics
Packet size 500 Bytes
Packet size 100 Bytes
26
Analytical evaluation of energy savings

• Pa Power consumed by the ONU during Active
  state
• Plpi Power consumed by the ONU during Low
  Power Idle state
• Ta Time spent in Active state
• Ts Time spent in Sleep state
• Tlpi Time spent in Low Power Idle state
• Tw Time spent in wake state
• ONUcycletime SONUtimespentinindividualstates
  Ta Ts Tlpi Tw
• Let the energy consumed by the ONU with sleep be
  denoted by Es and the one without Sleep technique
  be Ews
• EwsPa(Ta T s Tlpi Tw)
• The energy consumed by the ONU when it is has
  the Sleep technique implemented in it, is given
  by the following equation.
• EwsPa(TaTs Tw) PlpiTlpi
• Energy Savings ((Ea-Eb)/Ea)100
• Energy Savings ((Pa-Plpi)Tlpi/(Pa(TaTs
  Tlpi Tw)))100
• Consider Pa 10 Plpi

27
Generator consistency
Throughput Vs Packet size
28
Exponential inter-arrival time results
29
Conclusion

• This thesis proposed and implemented a sleep mode
  technique in the data link layer for Ethernet
  PONs in Altera Stratix 4GT FPGA. The sleep
  technique is based on the FSM implementation
  written in Verilog HDL.
• The FSM switches the ONU on and off based on
  the sleep request en-coded explicitly through out
  green header implementation based on the sleep
  time, low power idle time and wake time are all
  based on IEEE 803.az standard.
• The analytical evaluation for the proposed
  design provides Energy efficiency of 75 , when
  the power during active state is ten times the
  power at low power state. The results obtained
  after the implementation coincides with the
  analytical results. Hence substantial energy
  savings is achieved with our implementation.
• The implementation was performed on the testbed
  setup in two different modes local loopback and
  internal loopback. Similar results were obtained
  for both the configurations. For the
  implementation with standard values as defined in
  IEEE 803.az
• Additionally, a negative exponential
  inter-arrival module was developed. This is
  integrated in the generator to emulate the inter
  packet arrival times. So that packet arrivals can
  be modeled with various statistical distributions.

30
Future scope

• For the ONU to have low power consumption, it has
  to remain in the sleep mode as long as possible.
  The longer the better. But for guaranteed quality
  of service (QOS), the buffers should be large
  enough to store all the packets which arrive even
  when the ONU is sleeping.
• They buffers should be intelligently managed
  both in terms of buffer size and the number of
  buffers. This in itself is an interesting task
  which requires buffer optimization mainly due to
  the limited resources available in the FPGA.
• In the real time scenario, implementation of
  the buffer(s) would be inevitable because
• Numbers of users are ever increasing.
• Traffic is increasing.
• Bandwidth requirements are rising.
• QOS has to be guaranteed.
• Taking all the above into considerations, a
  dynamic sleep protocol is required. This should
  not only manage the buffers, but also should
  synchronize with both the OLT and ONU.

31
Grazie