Interconnect Efficient LDPC Code Design

1
Interconnect Efficient LDPC Code Design

• Aiman El-Maleh Basil Arkasosy Adnan Al-Andalusi
  
• King Fahd University of Petroleum Minerals,
  Saudi Arabia

2
Outline

• Motivation
• LDPC Code Overview
• LDPC Codes and Cycles
• Cycles Detection Algorithm
• Area Constrained LDPC code Design
• Experimental results
• Conclusions

3
Motivation

• LDPC codes belong to a family of error correction
  systems with performance close to
  information-theoretic limits.
• Selected for next-generation digital satellite
  broadcasting standard (DVB-S2), ultra high-speed
  Local Area Networks (10Gbps Ethernet LANs).
• LDPC codes inherently more amenable to
  parallelization.
• LDPC code design based on random code generation
  results in long interconnect wires, lower speed,
  higher power and less area utilization.
• Objective to design interconnect-efficient LDPC
  codes with relatively good error correction
  performance.

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LDPC Codes Overview

• LDPC codes linear block codes decoded by
  efficient iterative decoding.
• An LDPC parity check matrix H represents the
  parity equations in a linear form
• codeword c satisfies the set of parity equations
  H c 0.
• each column in the matrix represents a codeword
  bit
• each row represents a parity check equation

c0 ? c1 ? c3 0 c1 ? c2 ? c4 0 c2 ? c3 ? c5
0 c3 ? c3 ? c6 0
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LDPC Codes Overview

• LDPC codes can be classified as regular or
  irregular
• H matrix is (Wc,Wr)-regular
• each row contains same number Wr
• each column contains same number Wc.
• LDPC codes represented by Tanner Graphs
• two types of vertices Bit Vertices and Check
  Vertices
• Code Rate ratio of information bits to total
  number of bits in codeword

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LDPC Codes Cycles

• Existence of cycles (loops) in tanner graphs of
  LDPC codes impact performance.
• A cycle of size K is a closed path of K edges
  visiting a vertex more than once, while visiting
  each edge in this path only once.
• Possible cycles are of even sizes, starting by
  four.

4-loop
6-loop
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Cycle Detection Algorithm

• Checking if an edge between the bit node i and
  the check node j creates a four loop
• Find the set of all bit nodes K to which check
  node j is connected.
• For each bit node k in K (k ? i), find all the
  check nodes L that are connected to that node.
• For each check node l in L (l ? j), find all the
  bit nodes M that are connected to that node.
• If node i is in M, then a four loop is detected

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Area Constrained LDPC Code Design

• Randomly designed LDPC codes achieve good error
  correction performance.
• Wire lengths in decoders can become very large.
• Objective to design LDPC codes with constrains on
  interconnect wire length
• considerable decrease the signal delay
• lowering interconnect routing congestion
• reducing chip area
• reducing power dissipation
• Designed LDPC codes with 1024 bits and ½ rate.

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Area Constrained LDPC Code Design

• Bit check nodes laid out in a two-dimensional
  structure.
• Connections btw. bit check nodes constrained
  within a window of rows columns.
• Guarantees wire length bounded by a maximum
  length.
• Example
• Window(R,C) (2,3).
• Bit node 16 can only connect to check nodes
  (4,5,6,8,9,10).

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Set of Check Nodes for a Bit Node
NxM bit nodes, NxM/2 check nodes, window
constraint (R, C)
Row?i/M? Col i mod M Vertical
DomainR/2 Assigned check node
?(ColRowM)/2? t 1 for each t ?
Vertical Domain if (assigned check node
(t-1) (M/2)) lt No. check nodes Then
assigned check node assigned check node ((t
-1) (M/2)) Add_Horizontal( assigned check
node , Row (t-1) ) if (assigned check
node t (M/2)) ? 0 Then assigned check
node assigned check node (t (M/2))
Add_Horizontal( assigned check node , Row - t
) t t 1
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Set of Check Nodes for a Bit Node
Add_Horizontal (assigned check node ,
Row) Horizontal Domain (C-1/)2 add the
assigned check node k 1 for each k ?
Horizontal Domain if (assigned check node
k) lt ((M/2) (Row 1)) Then add the
check node assigned check node k if
(assigned check node - k) ? ((M/2) Row) Then
add the check node assigned check node
- k k k 1
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Experimental Results

• Designed LDPC codes (3,6)-regular with 1024 bits
  and ½ rate.
• LDPC codes randomly generated under given
  constraints.
• Five LDPC codes for each criteria considered
  best selected
• 4-loop free (4L),
• 6-loop free (6L),
• minimized 8-loop (M8L),
• window constrained minimized 8-loop (WM8L).
• LDPC codes with 32x32 layout of bit nodes and
  32x16 layout of check nodes.
• A constraint window (R, C)(16, 15) is assumed.

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Experimental Results

• FER performance using simulations at different
  SNR points
• stopping criteria of 200 frame errors at SNR?2
  and 200,000 code words for SNRgt2.
• Iterative decoding performed for 64 iterations.
• Hardware comparisons based on VHDL model with
  parallel implem. of LDPC decoder from H matrix
• functions of check and variables nodes a dummy
  single gate
• Synthesis performed using Xilinx synthesis tools
  on Xilinx Spartan3 XC3S5000-fg900 FPGA optimized
  for area.

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FER Comparison of LDPC codes
SNR
FER
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Loop Count and Synthesis Results
LDPC Code Structure No. of Loops No. of Loops No. of Loops Synthesis Synthesis
LDPC Code Structure No. of Loops No. of Loops No. of Loops Slices used out of 33,280 Delay (ns)
LDPC Code Structure 4 6 8 Slices used out of 33,280 Delay (ns)
4L 0 172 1273 2,562 14.19
6L 0 0 1300 2,562 14.34
M8L 0 0 226 2,562 13.10
WM8L 0 0 870 2,527 11.88
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Post Place and Route Snapshots of Synthesized
LDPC codes
M8L
WM8L
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Conclusions

• Investigated design of interconnect-efficient
  LDPC codes that reduce area and delay of decoder
  while maintaining good error correction
  performance.
• LDPC codes designed with loop constraints
  window constraint on interconnect wire length.
• Demonstrated possibility to deign LDPC codes that
  are interconnect efficient
• small performance impact compared to randomly
  unconstrained generated LDPC codes.
• Less delay and routing congestion