Dynamically Reconfigurable Architecture for Third Generation Mobil Systems

1
Dynamically Reconfigurable Architecture for Third
Generation Mobil Systems

• Ahmad Alsolaim

Ohio University School of of Electrical
Engineering and Computer Science
2
Outline

• Introduction
• Third and Future Generations Mobile Systems
• WCDMA Baseband Signal Processing
• Computing Architecture Models
• Dynamically Reconfigurable Architecture DRAW !
• Dynamically Reconfigurable Architecture Design
• Mapping Examples
• Conclusion and Recommendations

3
Introduction

• Wireless broadband access techniques challenges
• Access mechanisms,
• Energy conservation,
• Low error rate,
• Transmission speed characteristics,
• Small size, Light weight, Long battery life, and
  Low cost.

4
Introduction

• Adaptability
• Many standards
• WCDMA, IS-95, cdma2000, ...etc
• Flexibility
• Many services within one standard
• voice, audio/video, data, GPS, etc.

5
Introduction (Contd)

• Future generations mobile terminals will be
  implemented with a System-on-a-Chip (SoC)

6
Introduction (Contd)

• Reconfigurable Architectures
• Fine-grain reconfigurable architectures
• Commercial FPGAs like Xilinx 4000 FPGA family,
  and Altera Flex 8000 FPGA family
• Coarse-grained architectures
• PADDI-2, PipeRench, Morphosys, Grap, KressArray,
  and Colt.
• Special commercial RA for communication
  applications
• QuickSilver , and Chameleon CS2000

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Third and Future Generations Mobile Systems
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Characteristics of WCDMA

• WCDMA standard has two modes for the duplex
  method. A Frequency Division Duplex (FDD) and
  Time Division Duplex (TDD).

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Characteristics of WCDMA (Contd)
Channel bandwidth 5 MHz
Duplex mode FDD and TDD
Chip rate 3.84 Mcps
Frame length 10 ms
Spreading modulation Balanced QPSK (downlink) Dual-channel QPSK (uplink)
Data modulation QPSK (downlink) BPSK (uplink)
Channel coding Convolutional and turbo codes
Coherent detection User time multiplexed pilot (downlink and uplink), common pilot in the downlink
Spreading factors 4256 (uplink), 4512 (downlink)
Spreading (downlink) OVSF sequences for channel separation Gold sequences 218-1 for cell and user separation (truncated cycle 10 ms)
Spreading (uplink) OVSF sequences, Gold sequence 241 for user separation (different time shifts in I and Q channel, truncated cycle 10 ms)
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Characteristics of WCDMA (Contd)
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Future Generations wireless Systems

• Future Generation Mobile Systems

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WCDMA Baseband Signal Processing
13
WCDMA Baseband Signal Processing
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WCDMA Baseband Signal Processing
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WCDMA Baseband Signal Processing

• Baseband Signal Processing Requirements

Function Number of Million Instructions per Second (MIPS) _at_ 384 Kbps
Digital Filters (RRC, Channelization) 3600 MIPS
Searcher (Frame, slot, delay path, etc.) 1500
RAKE Receiver 650
Turbo coding 52
Maximal Ratio Combiner (MRC) 24
Channel estimation 12
AGC, AFC 10
De-interleaving, rate matching 14
TOTAL 5860
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WCDMA Baseband Signal Processing

• Digital Filters

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WCDMA Baseband Signal Processing

• Searcher

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WCDMA Baseband Signal Processing

• MATLAB Simulation of PSCH searcher

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WCDMA Baseband Signal Processing

• RAKE Receiver and Maximal Ratio Combining

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WCDMA Baseband Signal Processing

• RAKE finger correlation arm

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WCDMA Baseband Signal Processing

• Turbo encoding

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WCDMA Baseband Signal Processing

• Turbo decoder

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WCDMA Baseband Signal Processing

• MATLAB turbo simulation

24
Computing Architecture Models

• Current computer architectures
• ASIC implementation
• DSP Implementation
• FPGA Implementation

25
Computing Architecture Models

• Why Dynamically Reconfigurable Computing?

26
Computing Architecture Models

• Why Dynamically Reconfigurable Computing

27
Computing Architecture Models

• Why Dynamically Reconfigurable Computing
• IP-based Mapping
• Flexibility
• Area, Power, and Cost

28
Dynamically Reconfigurable Architecture

• The Dynamically Reconfigurable Architecture
  (DRAW) Model

29
Introducing DRAW

• DRAW consists of
• Coarse-grained Dynamically Reconfigurable
  Processing Units (DRPUs)
• Communication Network
• Dedicated I/O
• Fast Dynamic Reconfiguration

30
Introducing DRAW
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Introducing DRAW

• DRAW consists of an array of parallel operating
  coarse-grained Dynamically Reconfigurable
  Processing Units (DRPUs)
• Regular and Simple Array Structure
• Special Processing Units
• Configurable Linear Feedback Shift Register
  (CLFSR)
• Configurable Spreading Data Path (CSDP)
• RAM and FIFO Storage
• Scale and Delay

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Designing DRAW
33
Designing DRAW

• Operation Profile

34
Designing DRAW

• Operation Profile

35
Designing DRAW

• Operation Profile

36
Designing DRAW

• Operation Profile

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Designing DRAW

• Review of 3GPP WCDMA
• A transmitter block diagram

38
Designing DRAW

• Review of 3GPP WCDMA
• A receiver baseband block diagram

39
Designing DRAW

• Review of 3GPP WCDMA
• 3GPP downlink scrambling code generator

40
Designing DRAW

• Review of 3GPP WCDMA
• De-spreading circuit for QPSK

41
DRAW

• Dynamically Reconfigurable Processing Unit (DRPU)
• One 16-bit Dynamically Reconfigurable Arithmetic
  Processing unit (DRAP),
• One Configurable Spreading Data Path (CSDP),
• One Configurable linear Feedback Shift Register
  (CLFSR),
• One DRPU controller,
• One dual port RAM/FIFO, and
• Two I/O interfaces.

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DRAW

• DRPU

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DRAW

• Dynamically Reconfigurable Arithmetic Processing
  unit (DRAP)

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DRAW

• DRAP operations

Operation Description
1 MUL 2s complement multiplication
2 ADD 2s complement addition
3 SUB 2s complement subtraction
4 SHIFT Logic arithmetic shift
5 AND Bit-wise AND
6 NAND Bit-wise NAND
7 OR Bit-wise OR
8 NOR Bit-wise NOR
9 XOR Bit-wise XOR
10 XNOR Bit-wise XNOR
11 NOT Bit-wise NOT
12 MAX Maximum
13 MIN Minimum
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DRAW

• The DRPU controller

46
DRAW

• The RAM/FIFO Unit

47
DRAW

• The Configurable Spreading Data Path (CSDP)

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DRAW

• The Configurable Spreading Data Path (CSDP)

49
DRAW

• Communication Network
• Dynamically Reconfigurable
• Deterministic/Non deterministic communications

50
DRAW

• Dedicated I/O

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DRAW

• Fast Dynamic Reconfiguration

52
Mapping Examples
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Mapping Examples
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Mapping Examples

• Mapping M-sequence generator
• Mapping Gold-Code generator
• Mapping an FIR filter

55
Mapping Examples

• Mapping M-sequence generator

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Mapping Examples

• Mapping M-sequence generator (3-Stage)

57
Mapping Examples

• Mapping M-sequence generator (5-Stage)

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Mapping Examples

• Mapping Gold-Code generator

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Mapping Examples

• Mapping Gold-Code generator

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Mapping Examples

• Mapping an FIR filter

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Mapping Examples

• Mapping an FIR filter

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Mapping Examples

• Mapping an FIR filter

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Mapping Examples

• Mapping an FIR filter

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Conclusion and Recommendations

• There is a strong need for Dynamic Reconfigurable
  Architectures (DRA) as a part of SoC for future
  wireless mobile devices
• DRA provide
• Smaller physical size,
• Longer batteries,
• Lower cost, and
• Flexibility

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Conclusion and Recommendations

• The DRA must provide fast configuration/Reconfigur
  ation
• DRAW uses a dedicated routing lines for the
  configuration bits.
• DRAW uses a hierarchal reconfiguration structure
• DRAW uses four shared context of configuration
  sets.

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Conclusion and Recommendations

• The DRA must provide efficient processing
  elements
• DRAW provides a 16-bit based dynamically
  reconfigurable processing units (DRPUs)
• The DRPU provides
• Multiplication (2s Complement)
• ALU
• Storage
• Scale and Delay
• Spreading/De-spreading
• Linear Feedback Shift Register
• Rotate and shift

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Conclusion and Recommendations

• Recommendations for Future Work
• Auto Mapping
• Interfacing to other components for the SoC
• Improve the design for power saving
• Auto generation of a DRA design guidelines from a
  set of functional-descriptions.

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Contributions During this Ph.D.

• Publications
• Journal Papers
• Jürgen Becker, Ahmad Alsolaim, Janusz Starzyk,
  and Manfred Glesner. A Parallel Dynamically
  Reconfigurable Architecture Designed for
  Application-specific Hardware/Software Systems in
  Future Mobile Communication, In The Journal of
  Supercomputing, Kluwer Academic Publishers,
  October, 2000
• Conferences Papers
• A. Alsolaim, J. Becker, M. Glesner, J. Starzyk.
  Architecture and Application of a Dynamically
  Reconfigurable Hardware Array for Future Mobile
  Communication Systems, In Proc. of IEEE
  Symposium of Field-Programmable Custom Computing
  Machines (FCCM00), Napa, USA, April 17-19, 2000,
  Page(s) 205 -214
• J. Becker, M. Glesner, A. Alsolaim, J. Starzyk
  Fast Communication Mechanisms in Coarse-grained
  Dynamically Reconfigurable Array Architectures
  Proceedings of Second International Workshop on
  Engineering of Reconfigurable Hardware/Software
  Objects (ENREGLE00, in conjunction with PDPTA
  2000), Las Vegas, USA, June 26-29, 2000.

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Contributions During this Ph.D.

• Conferences Papers
• A. Alsolaim, J. Becker, M. Glesner, J. Starzyk.
  A Dynamically Reconfigurable System-on-Chip
  Architecture for Future Mobile Digital Signal
  Processing, In Proc. of X European Signal
  Processing Conference (EUSIPCO 2000), Tampere,
  Finland, September 4-8, 2000
• Szabo, A. Manolescu, A. Alsolaim, A. Glesner,
  M. Performance simulation of a RAKE receiver for
  direct sequence spreading spectrum communication
  systems, International Semiconductor Conference,
  2000. CAS 2000 Proceedings., Page(s) 245 -248
  vol.1
• Alsolaim, A. Starzyk, J. Dynamically
  Reconfigurable Solution in the Digital Baseband
  Processing for Future Mobile Radio Devices,
  Proceedings of the 33rd Southeastern Symposium on
  System Theory, 2001. Page(s) 221 -226

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Contributions During this Ph.D.

• Conferences Papers
• A.Szabo, A.M. Manolescu, A. Alsolaim, M.Glesner,
  Direct Sequence Spread Spectrum Communication
  Systems in a Multipath Fading Channel. RAKE
  Receiver Performance Analysis, Balkan Conference
  on Signal Processing, Communications, Circuits
  and Systems, 2000, Istanbul
• Mingwei Ding, Ahmad Alsolaim, and Janusz Starzyk,
  Designing and Mapping of a Turbo Decoder for 3G
  Mobile Systems Using Dynamically Reconfigurable
  Architecture, The 2002 International Conference
  on Engineering Of Reconfigurable Systems And
  Algorithms ERSA'02 June 24-27, 2002 Monte Carlo
  Resort, Las Vegas, Nevada, USA

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Contributions During this Ph.D.

• Proposals
• Dynamically Reconfigurable Architecture for 3G
  Mobil Communication Systems, Submitted to NSF,
  April. 1999.
• Dynamically Reconfigurable Architecture for
  Third Generation Mobil Systems, Submitted to
  NSF, May 2001.
• Joint Research
• One academic year at Darmstadt University of
  Technology, Institute of Microelectronic Systems.
• One Master of science thesis Design and
  Simulation of a Dynamically Reconfigurable
  Hardware Architecture for Future Mobile
  Communication System By Thilo Pionteck.
• Arrangement for a lecture by Dr. Mohammed
  Al-Ogeeli titled A Simple Alternative For
  Storage Allocation in High-Level Synthesis at
  the Institute of Microelectronic Systems,
  Darmstadt, Nov. 1999.

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Contributions During this Ph.D.

• Co-chaired with Dr. Mohammed Al-Ogeeli the first
  Reconfigurable System-on-a-Chip (RSoC) workshop
  at King Saud University, Riyadh, Saudi Arabia.
• Keynote Speakers
• Prof. Janusz Starzyk
• Prof. Manfred Glsner
• Dr. Jurgen Becker
• Tough a senior level VHDL Class. EECS 414 VHDL
  Design at the School of EECS, Ohio University.
• Was the recipient of Stocker Scholarship for the
  academic year 2001-2002.

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QA

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