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Putting Formal Description of Software Architecture in Practice: Good News, Bad News. Paola Inverardi UNIVERSITA DEGLI STUDI DELL AQUILA – PowerPoint PPT presentation

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Title: Putting%20Formal%20Description%20of%20Software%20Architecture%20in%20Practice:%20Good%20News,%20Bad%20News.


1
Putting Formal Description of Software
Architecture in Practice Good News, Bad News.
  • Paola Inverardi

UNIVERSITA DEGLI STUDI DELLAQUILA Area
Informatica, Facolta di SSMMNN
2
Brief history of our work in SA
  • Formal description of SA via CHAM
  • Behavioral Analysis of the SA
  • algebraic analysis and finite state modeling
  • validation and quantitative analysis based on
    FSTM

3
Our experience
  • Modelling SA for three telecommunication
    companies
  • UML as ADL
  • Poor dynamics descriptions

4
DYNAMICS
  • A model of all possible system behaviours
  • state diagrams for manageable processes
  • implicit parallel notation for composite
    processes-. P1P2Pn
  • No explicit representation due to state explosion
  • Sequence diagrams/MSCs

5
ITALIAN TELECOM NETWORK ARCHITECTURE
WDM
WL
WL
STM-16 Ring
STM-16 Ring
ADM
ADM
ADM
ADM
ADM
ADM
ADM
ADM
ADM
National level
ADM
ADM
STM-4/16
STM-4/16
SXC 4/1
SXA
SXA
SXA
ADM
ADM
STM-1/4
ADM
STM-4/16
Regional level
ADM
ADM
STM-1/4
ADM
ADM
ADM
ADM
ADM
STM-1/4
ADM
ADM
ADM
ADM
City level
ADM
6
GOALS
  • Study of the SXA Cross Connettor.
  • Development of a SA description (formal /
    semi-formal) to allow quantitative analysis
  • Try different description techniques. (UML,
    ADL, Process Algebras)
  • The identification and structuring of the
    information necessary to produce a performance
    model.
  • Reverse Engineering. Process

7
SXA SYSTEM SOFTWARE CONFIGURATION
TLECOMM. PROVIDER
OSI STACK
COMMAND HANDLER
DATABASE MANAGER
LOCAL TERMINAL
SYSTEM FUNCTION
Database MIB
XCONN
8
SXA SYSTEM HARDWARE CONFIGURATION
ET-MUX
T-MUX
T-MUX
ES-CORE working
ES-CORE protection
ET-MUX
T-MUX
T-MUX
C-CORE
Rack IO
Rack IO
Rack IO
Rack CENTRAl
9
SOFTWARE LAYERS
External Interfaces
FM
LPS
DR
XCONN
TM
TIM
CM
PM
DN
EPS
Global Functions
Shelf Functions
Periferal Functions
Unit Handler
System
Base
Hardware unit
10
HARDWARE LAYERS
ES-CORE Protection
C-CORE

GLOBAL
ES-CORE Working
. Timing
MSCU
MSCU

SHELF
8 ETMSU
PSCU
LAN HUB

PERIFERAL
C-LAN
2 TSU
PSCU
PSCU
2 TSU
PSCU
2 TSU
DPS
TDU
DPS
TDU
ASU
Phisical ports
ASU
Phisical ports
ASU
Phisical ports
TDU
T-MUX 1
ET-MUX 1
T-MUX16 1
T-MUX n lt 30
ET-MUX n lt 16
T-MUX16 n lt 8
11
XCONN LAYERS
GXC
Global
Shelf
SSXC
CXC
TXC
BXC
STXC
SAXC
Periferal
PSXC
PTXC
12
REVERSE ENGINEERING PROCESS
System Domain Study
System Function XCONN Domain Study
Architectural Description
Functional Partition
13
DOMAIN SYSTEM STUDY
Domain System Study
Components High-Level Documentation
XCONN Domain Study
Domain System Study
High-Level Sequence Diagrams (UML)
Interviews
Architectural Description
Functional Partition
14
XCONN DOMAIN STUDY
Previous phases
Domain System Study
Exchanched Messages lists
Components detailed description
XCONN Domain Study
XCONN Domain Study
Stereotyped class diagrams (UML)
Deployment Diagram (UML)
Architectural Description
Functional Partition
15
STEREOTYPED CLASS DIAGRAM (UML) SYSTEM
16
STEREOTYPED CLASS DIAGRAM (UML) SYSTEM FUNCTION
XCONN
17
ARCHITECTURAL DESCRIPTION
Previous activities results
System Domain study
MSG abstraction
Components Detailed Description
architectural description
XCONN domain study
Static description of components with DARWIN
SDL Code and Diagrams
Architectural description
Components Behavioral description by the FSP
process algebra
Functional partition
Feedback on previous activities results
18
STATIC DESCRIPTION WITH DARWIN
Components hierarchy
19
STATIC DESCRIPTION WITH DARWIN
Graphic Description of the SAXC component
SAXC
cxc0
cxc1
bxc1
bxc0
txc1
txc2
txcn
20
GRAPHIC SDL
SDL STATE
INPUT MESSAGES
OUTPUT MESSAGES
21
Sub-structure of the BXC process
22
FSP Description of the BXC process
23
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24
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25
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26
FUNCTIONAL PARTITION
System Domain Study
Previous activities results
XCONN Domain Study
Messagge Sequence Chart (MSC)
Functional Partition
SDL Diagrams and code
Architectural Description
Activity diagrams (UML)
Functional Partition
27
MESSAGE SEQUENCE CHART (MSC)
Components istances
automata transition.
FSP processes state before performing the action
FSP process state after performing the action
28
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29
COLLABORATION DIAGRAMS (UML)
30
Summarizing
  • Issue of complexity Have clear in mind what the
    SA has to be for
  • Domain specific ADL, complementing standard
    notations with ad hoc notations, e.g. FSP
  • Predictive analysis and evaluation of the
    architectural choices
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