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Exception Handling (2)

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Title: Exception Handling (2)


1
Exception Handling (2)
2
68000 Exception Handling
  • The 68000s exception classification
  • Register that support OS and exceptions
  • Protecting OS memory
  • The various exceptions
  • The exception vectors

3
The 68000s family exceptions
4
Supervisory State Registers
Registers across The processor Family
5
Registers
  • 68000
  • SSP Supervisor Stack Pointer
  • System Byte of Status Word
  • 68010 adds
  • Vector Base Register
  • Source Function Code
  • Destination Function Code
  • etc

6
Supervisor Memory Space
7
Exceptions and Interrupts
  • Reset
  • Externally Generated
  • Force both the RESET and HALT pins low for at
    least 10 clock cycles
  • Force the 68000 into a known start-up state
  • No RTE

8
Exceptions and Interrupts
  • Bus Error
  • Externally Generated
  • Initiated by hardware driving BERR pin low
  • A catchall exception
  • Can be used to indicated non-populated memory has
    been addressed

9
Exceptions and Interrupts
  • Interrupt
  • Hardware generated on pins IPL0, IPL1, IPL2
  • Pins activated indicated level of interrupt
  • Bits 8, 9, 10 of the status word indicates level
    of interrupt needed for service
  • Interrupting device generates level code through
    a 8-line-to-3-bit encoder

10
Interrupt Hardware
11
Interrupt HW Level encoder
12
Exceptions and Interrupts
  • Address Error
  • Exception occurs when 68000 attempts to access a
    16-bit word or 32-bit longword at an odd address
  • Consider
  • LEA 7000,A0 Load A0 with 00 7000
  • MOVE.B (A0),D0 Load D0 with byte at (A0)n incr
  • MOVE.W (A0),D0 Load D0 with word
  • Final instruction has A0 containing 7001

13
Exceptions and Interrupts
  • Illegal Instruction
  • What happens when you try to execute and op-code
    that is not defined?
  • 8-bit uprocessor days
  • 68000?
  • Illegal Instruction Exception

14
Exceptions and Interrupts
  • Divide by Zero
  • Trying to divide by 0 generates this exception
  • CHK Instruction
  • Check Register against bounds
  • CHK D1,D0 generates an exception if
  • D0(015) lt 0
  • D0(015) gt D1(015)
  • Point useful for compiler writers

15
Exceptions and Interrupts
  • Privilege Violation
  • Processor in user state (S-bit is clear)
  • Attempt to execute a privileged instruction
  • Trace
  • Controlled by the trace bit of the status word
  • Contents of all registers output after each
    instruction

16
Exceptions and Interrupts
  • Line 1010 Emulator
  • Allow creation of special instructions
  • When this op code is encountered an exception
    occurs
  • Remaining bits of instruction word can be used to
    further specify user created instruction
  • Line 1111 Emulator
  • A second version

17
Exceptions and Interrupts
  • Un-initialized Interrupt Vector
  • When a 68000 device causes and interrupt
  • During IACK device supplies ID
  • If not yet initialized 0F is sent so device can
    be initialized
  • 68000 Devices respond with 0F when reset

18
Exceptions and Interrupts
  • Spurious Interrupt
  • IACK generated but no response?
  • Prevents hanging when no device responds to IACK
    after an IPL0-IPL2 pin pulled low
  • TRAP (Software Interrupt)
  • TRAP x where x is from 0 to 15 (0 to F)
  • Allows creation of unique instructions

19
Exceptions and Interrupts
  • TRAPV Instruction
  • Trap on overflow
  • IF V1 THEN exception ELSE continue
  • Double Bus Fault
  • Example A bus error occurs and while responding
    to this a second bus error occurs?
  • 68000 halts!!!

20
Exception Vectors
  • 256 longwords (512 words)
  • Extend form address 00 0000 to 00
    03FF

21
Exception Vector Table
  • Table located in low memory
  • Schemes allow relocation to other addresses

22
  • How would you implement the table in memory?
  • How would you allow the movement of the table to
    other addresses of memory?
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