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Workshop Objectives and Guidelines

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Victor Zhirnov ITRS Emerging Research Logics Devices workshop September 21, 2012 Bordeaux, France Some briefing on ADI s approach to process technologies Key points ... – PowerPoint PPT presentation

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Title: Workshop Objectives and Guidelines


1
Workshop Objectives and Guidelines
  • Victor Zhirnov
  • ITRS Emerging Research Logics Devices workshop
  • September 21, 2012
  • Bordeaux, France

2
ERD Logic Editorial Team
Adrian Ionescu / EPF Lausanne George Bourianoff /
Intel Corp. Atsuhiro Kinoshita / Toshiba Shamik
Das / MITRE Corp. An Chen / GFLOBALFOUNDRIES Jim
Hutchby / SRC Victor Zhirnov / SRC
3
Workshop Objective
  • The primary purpose of the Emerging Memory
    Workshop is to evaluate the potential and status
    of each specific logic technology option
    identified by the ITRS ERD Working Group in the
    2011 ITRS.
  • For the first time, the scope of the analysis of
    ERD Logic device is expanded to include
    non-logic applications
  • analog, RF, mixed-signal
  • More-than-Moore
  • In 2012 a joined ERD-RF/AMS taskforce fromed to
    explore
  • Analog/RF properties of ERD devices
  • New functionalities for RF/AMS applications

4
Analog/RF/Mixed Signal Primitives (exploration of
the obvious?)
Material for discussion, provided by David
Robertson, Analog Devices david.robertson_at_analog.c
om
  • September 2012

5
Semiconductor Technology Stack
  • Each regime has its own set of expertise
    innovation can occur at any layer, though many of
    the most interesting innovations occur across
    multiple layers.

Application Technology
System Technology
Architecture/Topology
Circuit Technology
Reflecting on this space-- particularly for
disruptive innovation in process and device
technology
Device Technology
Process Technology
6
Problem Statement
  • Given that a 20nm FINFET makes a better
    (faster/smaller) transistor, does it make a
    better
  • Microprocessor ?
  • Radio?
  • A/D Converter ?
  • The lithography march has provided the
    semiconductor industry with continuous advance
    (on a geometric or even exponential pace in many
    dimensions)--
  • Should we expect that to continue?
  • What about non-lithographic innovation (e.g.
    carbon nanotubes)

7
The Notion of Circuit Primitives
  • Microprocessor, Radio, ADC are at too high a
    level to map directly from transistor
    performance
  • If transistors are our atoms, we need to think
    about what constitutes the molecules . . .
  • Digital Primitives Logic Gate, Latch, Memory
    Cell, buffer
  • Consider primitives in other domains Analog,
    RF, Power, Sensor, Transducer
  • Primitives can then be combined to produce
    functional blocks
  • Proposed definition for a primitive-- no more
    than 4-6 transistors (exceptions will have to be
    made)

8
Looking at Process Technology Advancement
through Primitives
  • Digital Figures of Merit
  • -- decreased area (per function) increased
    density
  • -- decreased power (per function)
  • -- increased speed
  • Starting to track ROBUSTNESS often reflected in
    a error probability per operation or bit error
    rate-- in many ways this is a digital proxy
    for dynamic range . . . .

9
Looking at Process Technology Advancement
through Primitives
  • Analog/RF/Mixed Signal Figures of Merit
  • -- increased dynamic range lowered noise
    (noise figure)
  • -- increased dynamic range increased
    compression/distortion ceiling (IIP3,
    distortion at a given power level, etc)
  • -- increased speed/bandwdith (fT, fmax)
  • -- decreased area (per function) increased
    density
  • -- decreased power (per function)
  • Note that for many of the analog areas, emphasis
    on dynamic range and bandwidth may still be much
    greater than physical density.

10
Elemental Functions (partial list)
  • Digital
  • Logic gate
  • Latch
  • Memory
  • Buffer/driver
  • Analog
  • Analog switch
  • Sample/hold (analog memory)
  • Gain element
  • Analog variable element
  • Data Conversion
  • Quantizer (comparator)
  • Matched elements
  • Power Management
  • Voltage conversion
  • Power switch
  • Energy storage
  • Sensors
  • Optical
  • Inertial
  • Magnetic
  • Temp
  • Passives
  • Capacitor
  • Inductor
  • Resistor
  • Transmission line
  • RF
  • Low noise amplifier
  • Power amplifier
  • Mixer
  • Oscillator
  • Antenna
  • Transducers/ Actuators
  • Optical
  • Mechanical

11
Primitive Profile 2- pager
  • Description provided for each primitive
  • Functional Description
  • Abstract Behavioral Representation
  • Inputs, Outputs, Performance Parameters
  • Test Bench
  • Examples of transistor implementations
  • Trend plots performance vs. time
  • Bibliography appropriate citations and useful
    references
  • One key challenge is to abstract the FUNCTION
    back from the transistor implementation
  • Consider the historic innovations at the
    PRIMITIVE level
  • CMOS gates replacing NMOS gates . . .

12
Reflection/Questions
  • Should we seek to minimize the number of
    primitives? (how big should our alphabet or
    periodic table be?)
  • Too many becomes clumsy
  • Too few may miss important functional differences

13
International Technology Roadmap for
Semiconductors (ITRS) Connection
  • ITRS Roadmapping Groups are predominantly
    semiconductor physicists and device engineers
    great for extrapolating lithography trends, and
    charting how transistor fT will evolve.
  • There is a good deal of effort put into thinking
    about how to map from process advances to
    device models again, this works reasonably
    well for extrapolating MOS transistor
    performance.
  • As the process technologies become more esoteric,
    and even move to some disruptive technologies,
    it is more difficult to establish whether a
    proposed new technology might represent an
    advance in functionality and performance.
  • This is a particularly interesting challenge for
    the emerging devices working group.

14
International Technology Roadmap for
Semiconductors (ITRS) Connection
Discrete Discrete Discrete Discrete Discrete Analog Analog Analog RF RF RF RF RF RF Data Conversion Data Conversion Data Conversion
  Logic Gate Latch Memory Sensor Actuator Analog switch Gain element Analog variable element RF LNA RF Power Amplifier Oscillator Frequency synthesizer Transmission line Antenna Sampler Quantifier Matched Elements
ERD Memory                                  
FeFET memory     YES NO NO                        
Nanomechanical YES YES MAYBE YES YES YES MAYBE NO     YES            
RedOx memory YES YES YES MAYBE NO YES YES YES             YES YES  
Mott memory         NO                        
Macromolecular memory     YES YES YES                        
Molecular memory     MAYBE YES NO                        
                                   
ERD Logic                                  
NWFET YES YES NO YES NO YES YES YES YES YES              
CNT FET YES YES YES YES YES YES YES YES YES YES              
graphene FET MAYBE       NO   YES   YES YES              
T-FET YES YES   NO NO   YES   YES YES              
spinFET         NO                        
spinMOSFET         NO                        
I-MOS MAYBE   NO NO NO                        
neg-C FET YES       NO                        
NEMS YES YES MAYBE YES YES   YES       YES            
Atomic switch YES YES YES YES YES MAYBE YES YES             YES YES  
Mott FET         NO                        
Spin wave devices         NO                        
Nanomagnetics         YES                        
Excitonic devices         NO                        
                                   
More-than-Moore                                  
Spin-torque oscillator                     YES            
NEMS resonantor                     YES            
Graphene RF transistor             YES   YES YES              
RTD RF mixer                                  
SET mixer                                  
Graphene rectifier                                  
15
Next step
  • Refining the mapping table
  • Current ERD list is inclusive and contains all
    devices
  • ERD Memory, Logic and More-than Moore
  • There are some obvious redundancies, e.g. NEMS,
    Redox Memory/Atomic Switch, Graphene Transistor
    etc.
  • Perhaps we should use principal physical
    mechanism instead of specific device name
  • On elemental functions, some of the current
    functions are more elemental than others

16
Next step (cont)
  • Two-pagers on Primitives
  • For each primitive, a simple circuit, test bench,
    and parameters of interest/figure of merit
  • Description of key challenges what
    applications/functions this primitive is a
    bottleneck.
  • Call for Inputs draft by end of July, first
    round of ideas to be shared by September 21
    workshop

17
ITRS workshop on Emerging Research Logic Devices
Bordeaux, France, September 21, 2012 (linked to
ESSRERC'12)
900 Overall workshop goals and objectives Victor Zhirnov / NCSU SRC USA
     
Session I Circuit Requirements Expectations for Emerging Research Devices Session I Circuit Requirements Expectations for Emerging Research Devices Session I Circuit Requirements Expectations for Emerging Research Devices
915 Digital Circuits David Frank / IBM - USA
945 Analog/Mixed Signal/ RF Circuits David Robertson / Analog Devices USA
1015 Programmable nanowire circuits for nanoprocessors Shamik Das / MITRE USA  
1045 Break Break
     
Session II Emerging Research Devices for Nanocircuits Session II Emerging Research Devices for Nanocircuits Session II Emerging Research Devices for Nanocircuits
1100 Tunnel FET Marc Heyns / IMEC Belgium
1130 CNT FET Subhasish Mitra / Stanford USA
1200 Graphene transistors Frank Schwierz / TU Ilmenau Germany
1230 1400 Lunch 1230 1400 Lunch 1230 1400 Lunch
1400 NEMS Devices Adrian Ionescu / EPF Lausanne Switzerland
1430 Atomic switch and memristor Dmitri Strukov / UC Santa Barbara USA
1500 MOTT FET Akihito Sawa / AIST USA
1530 Break Break
1545 Spin FET Viktor Sverdlov / TU Wien Austria
1615 Nanomagetic and all spin logic Wolfgang Porod / U Notre Dame USA
1645 Spin wave devices Alexander Khitun / UCLA USA
1715 Break Break
1730 Summary and wrap up Jim Hutchby/ SRC- USA
1800 Adjourn Adjourn
18
Workshop Questions Session 1
  • What/when are the presently envisioned routes and
    points of entry for emerging logic devices into
    commercial chips/systems/packages?
  • What are the major application drivers and
    does/should the emerging logic device roadmap
    differ substantially with respect to these
    drivers? e.g.
  • High-performance computing (e.g.,
    server/desktop/laptop multiprocessor)
  • Embedded applications (e.g., microcontroller or
    digital signal processor)
  • Mobile computing (e.g., low-power processor or
    System-on-Chip)
  • What are the circuit/system drivers for adoption
    of emerging devices for logic? e.g.,
  • Power advantages
  • On-chip computation vs. communication tradeoff
  • Are there recent developments of note in emerging
    devices that might have dual use for both
    information processing and other functions (e.g.,
    sensors, resonators, oscillators)?

19
Workshop Questions Session 2
  • What are the most significant research results
    during 2010-2012 regarding the subject device?
  • Speakers are asked to characterize devices as
    either FET replacement or non-FET devices.
  • For FET replacement devices, topics of interest
    include
  • What is the scaling potential (in terms of
    equivalent critical feature size and fundamental
    scaling limit) vs. scaled silicon CMOS?
  • What are the significant theoretical advantages
    and disadvantages vs. scaled CMOS? Including
  • spatial pitch and density
  • voltage scalability (including impacts of, e.g.,
    subthreshold slope)
  • speed and energy at device level and circuit
    level (e.g., for FO4 inverter)
  • What is the demonstrated state of the art today
    relative to theory?

20
Workshop Questions Session 2 (cont)
  • For non-FET devices, topics of interest
    include
  • What is the state variable?
  • What is the equivalent function being replaced
    (e.g., logic gate)?
  • How is the state or functional output
    communicated between devices? (e.g., direct
    transmission, spin-to-voltage conversion, etc.)
  • What are the estimated quantitative advantages
    and disadvantages, e.g.,
  • density (functions per sq. cm.)
  • computation speed and energy per computation
  • communications energy (J/bit or J/m/bit)
  • Is there a scaling scenario (e.g., geometrical
    scaling, functional scaling)?

21
Suggested topics for all devices
  • What are the major research and development
    issues to be addressed in order to achieve
    performance matching todays semiconductor
    devices and circuits?
  • What issues need to be addressed with respect to
    variation (including device-to-device variation,
    stochastic intra-device effects during operation,
    or any other sources of variability)?
  • What are the materials issues and manufacturing
    process issues that would need to be addressed
    (tools, metrology, etc.)?
  • What is the present status of modeling and
    simulation capabilities for the device and/or
    constituent materials?

22
Workshop Outcome
  • Inputs from the workshop will help the ITRS ERD
    Working Group to look at future long-term,
    post-CMOS trends in logic devices considerations.
  • The end goals are
  • To update and significantly improve the ITRS ERD
    Chapter, and, in particular, the Emerging
    Research Logic Section, for the 2013 Road Map
  • To address some of the ERD devices in the 2013
    ITRS RF/AMS Chapter and map the emerging devices
    to core circuit/process functions

23
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