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CPSC 321 Computer Architecture and Engineering Lecture 8 Designing a Multicycle Processor

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Title: CPSC 321 Computer Architecture and Engineering Lecture 8 Designing a Multicycle Processor


1
CPSC 321Computer Architecture and
EngineeringLecture 8 Designing a Multicycle
Processor
  • Instructor Rabi Mahapatra Hank Walker
  • Adapted from the lecture notes of John
    Kubiatowicz (UCB)

2
Recap A Single Cycle Datapath
Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rt
Rs
Rs
Rt
RegWr
ALUctr
5
5
5
MemtoReg
busA
Equal
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
3
Recap The Truth Table for the Main Control
4
Recap PLA Implementation of the Main Control
5
Recap Systematic Generation of Control
OPcode
Control Logic / Store (PLA, ROM)
Decode
microinstruction
Conditions
Instruction
Control Points
Datapath
  • In our single-cycle processor, each instruction
    is realized by exactly one control command or
    microinstruction
  • in general, the controller is a finite state
    machine
  • microinstruction can also control sequencing (see
    later)

6
The Big Picture Where are We Now?
  • The Five Classic Components of a Computer
  • Todays Topic Designing the Datapath for the
    Multiple Clock Cycle Datapath

Processor
Input
Control
Memory
Datapath
Output
7
Abstract View of our single cycle processor
Main Control
op
ALU control
fun
ALUSrc
Equal
ExtOp
MemWr
MemWr
MemRd
RegDst
RegWr
nPC_sel
ALUctr
Reg. Wrt
ALU
Register Fetch
Ext
Mem Access
PC
Instruction Fetch
Next PC
Result Store
Data Mem
  • looks like a FSM with PC as state

8
Whats wrong with our CPI1 processor?
Arithmetic Logical
PC
Reg File
Inst Memory
ALU
setup
mux
mux
Load
PC
Inst Memory
ALU
Data Mem
Reg File
setup
mux
mux
Critical Path
Store
PC
Inst Memory
ALU
Data Mem
Reg File
mux
Branch
PC
Inst Memory
cmp
Reg File
mux
  • Long Cycle Time
  • All instructions take as much time as the slowest
  • Real memory is not as nice as our idealized
    memory
  • cannot always get the job done in one (short)
    cycle

9
Reducing Cycle Time
  • Cut combinational dependency graph and insert
    register / latch
  • Do same work in two fast cycles, rather than one
    slow one
  • May be able to short-circuit path and remove some
    components for some instructions!

storage element
Acyclic Combinational Logic (A)
?
storage element
Acyclic Combinational Logic (B)
storage element
10
Basic Limits on Cycle Time
  • Next address logic
  • PC lt branch ? PC offset PC 4
  • Instruction Fetch
  • InstructionReg lt MemPC
  • Register Access
  • A lt Rrs
  • ALU operation
  • R lt A B

Control
MemWr
MemWr
MemRd
RegDst
RegWr
nPC_sel
ALUctr
ALUSrc
ExtOp
Reg. File
Exec
Operand Fetch
Mem Access
Instruction Fetch
PC
Next PC
Result Store
Data Mem
11
Partitioning the CPI1 Datapath
  • Add registers between smallest steps
  • Place enables on all registers

MemWr
MemWr
MemRd
RegDst
RegWr
nPC_sel
ALUSrc
ExtOp
ALUctr
Reg. File
Exec
Operand Fetch
Mem Access
Instruction Fetch
PC
Next PC
Result Store
Data Mem
12
Example Multicycle Datapath
Equal
nPC_sel
E
Reg File
A
PC
IR
Next PC
B
Instruction Fetch
Operand Fetch
  • Critical Path ?

13
Recall Step-by-step Processor Design
  • Step 1 ISA gt Logical Register Transfers
  • Step 2 Components of the Datapath
  • Step 3 RTL Components gt Datapath
  • Step 4 Datapath Logical RTs gt Physical RTs
  • Step 5 Physical RTs gt Control

14
Step 4 R-type (add, sub, . . .)
inst Logical Register Transfers ADDU Rrd lt
Rrs Rrt PC lt PC 4
  • Logical Register Transfer
  • Physical Register Transfers

inst Physical Register Transfers IR lt
MEMpc ADDU Alt Rrs B lt Rrt S lt A
B Rrd lt S PC lt PC 4
E
Reg. File
Reg File
Exec
PC
IR
Next PC
Inst. Mem
Mem Access
Data Mem
15
Step 4 Logical immed
inst Logical Register Transfers ORI Rrt lt
Rrs OR ZExt(Im16) PC lt PC 4
  • Logical Register Transfer
  • Physical Register Transfers

inst Physical Register Transfers IR lt
MEMpc ORI Alt Rrs B lt Rrt S lt A or
ZExt(Im16) Rrt lt S PC lt PC 4
E
Reg. File
Reg File
Exec
PC
IR
Next PC
Inst. Mem
B
Mem Access
Data Mem
16
Step 4 Load
inst Logical Register Transfers LW Rrt lt
MEMRrs SExt(Im16) PC lt PC 4
  • Logical Register Transfer
  • Physical Register Transfers

E
Reg. File
Reg File
Exec
PC
IR
Next PC
Inst. Mem
B
Mem Access
Data Mem
17
Step 4 Store
inst Logical Register Transfers SW MEMRrs
SExt(Im16) lt Rrt PC lt PC 4
  • Logical Register Transfer
  • Physical Register Transfers

inst Physical Register Transfers IR lt
MEMpc SW Alt Rrs B lt Rrt S lt A
SExt(Im16) MEMS lt B PC lt PC 4
E
Reg. File
Reg File
Exec
PC
IR
Next PC
Inst. Mem
B
Mem Access
Data Mem
18
Step 4 Branch
  • Logical Register Transfer
  • Physical Register Transfers

inst Logical Register Transfers BEQ if Rrs
Rrt then PC lt PC 4SExt(Im16) 00 else
PC lt PC 4
inst Physical Register Transfers IR lt
MEMpc BEQ Elt (Rrs Rrt) if !E then PC lt
PC 4 else PC ltPC4SExt(Im16)00
E
Reg. File
Reg File
A
Exec
PC
IR
Next PC
Inst. Mem
B
Mem Access
Data Mem
19
Alternative datapath (book) Multiple Cycle
Datapath
  • Miminizes Hardware 1 memory, 1 adder

PCWr
PCWrCond
PCSrc
BrWr
Zero
ALUSelA
MemWr
IRWr
RegWr
RegDst
IorD
1
Mux
32
PC
0
Zero
32
Rs
Ra
RAdr
5
32
32
Rt
Rb
busA
32
ALU
Ideal Memory
32
Instruction Reg
Reg File
5
32
ALU Out
4
Rt
0
32
Rw
WrAdr
32
1
32
Rd
Din
Dout
busW
32
busB
2
32
3
Imm
32
ALUOp
MemtoReg
ExtOp
ALUSelB
20
Our Control Model
  • State specifies control points for Register
    Transfer
  • Transfer occurs upon exiting state (same falling
    edge)

inputs (conditions)
Next State Logic
State X
Register Transfer Control Points
Control State
Depends on Input
Output Logic
outputs (control points)
21
Step 4 ? Control Specification for multicycle
proc
instruction fetch
IR lt MEMPC
decode / operand fetch
A lt Rrs B lt Rrt
LW
R-type
ORi
SW
BEQ
PC lt Next(PC,Equal)
S lt A fun B
S lt A or ZX
S lt A SX
S lt A SX
M lt MEMS
MEMS lt B PC lt PC 4
Rrd lt S PC lt PC 4
Rrt lt S PC lt PC 4
Rrt lt M PC lt PC 4
22
Traditional FSM Controller
next state
state
op
cond
control points
Truth Table
next State
control points
11
Equal
6
State
4
op
datapath State
23
Step 5 ? (datapath state diagram?? control)
  • Translate RTs into control points
  • Assign states
  • Then go build the controller

24
Mapping RTs to Control Points
IR lt MEMPC
instruction fetch
imem_rd, IRen
A lt Rrs B lt Rrt
decode
Aen, Ben, Een
LW
R-type
ORi
SW
BEQ
S lt A fun B
PC lt Next(PC,Equal)
S lt A or ZX
S lt A SX
S lt A SX
ALUfun, Sen
M lt MEMS
MEMS lt B PC lt PC 4
Rrd lt S PC lt PC 4
RegDst, RegWr, PCen
Rrt lt S PC lt PC 4
Rrt lt M PC lt PC 4
25
Assigning States
instruction fetch
IR lt MEMPC
0000
decode
A lt Rrs B lt Rrt
0001
LW
R-type
ORi
SW
BEQ
PC lt Next(PC)
S lt A fun B
S lt A or ZX
S lt A SX
S lt A SX
0100
0110
1000
0011
1011
M lt MEMS
MEMS lt B PC lt PC 4
1001
1100
Rrd lt S PC lt PC 4
Rrt lt S PC lt PC 4
Rrt lt M PC lt PC 4
0101
0111
1010
26
(Mostly) Detailed Control Specification
(missing?0)
State Op field Eq Next IR PC Ops Exec Mem Write-B
ack en sel A B E Ex Sr ALU S R W M M-R Wr
Dst
  • 0000 ?????? ? 0001 1
  • 0001 BEQ x 0011 1 1 1
  • 0001 R-type x 0100 1 1 1
  • 0001 ORI x 0110 1 1 1
  • 0001 LW x 1000 1 1 1
  • 0001 SW x 1011 1 1 1
  • 0011 xxxxxx 0 0000 1 0 x 0 x
  • 0011 xxxxxx 1 0000 1 1 x 0 x
  • 0100 xxxxxx x 0101 0 1 fun 1
  • 0101 xxxxxx x 0000 1 0 0 1 1
  • 0110 xxxxxx x 0111 0 0 or 1
  • 0111 xxxxxx x 0000 1 0 0 1 0
  • 1000 xxxxxx x 1001 1 0 add 1
  • 1001 xxxxxx x 1010 1 0 1
  • 1010 xxxxxx x 0000 1 0 1 1 0
  • 1011 xxxxxx x 1100 1 0 add 1
  • 1100 xxxxxx x 0000 1 0 0 1 0

-all same in Moore machine
BEQ
R
ORi
LW
SW
27
Performance Evaluation
  • What is the average CPI?
  • state diagram gives CPI for each instruction type
  • workload gives frequency of each type

Type CPIi for type Frequency CPIi x freqIi
Arith/Logic 4 40 1.6 Load 5 30 1.5 Store 4 10
0.4 branch 3 20 0.6 Average CPI 4.1
28
Controller Design
  • The state digrams that arise define the
    controller for an instruction set processor are
    highly structured
  • Use this structure to construct a simple
    microsequencer
  • Control reduces to programming this very simple
    device
  • ? microprogramming

29
Example Jump-Counter
i
i
0000
i1
Map ROM
None of above Do nothing (for wait states)
op-code
zero inc load
Counter
30
Using a Jump Counter
instruction fetch
IR lt MEMPC
0000
inc
decode
A lt Rrs B lt Rrt
0001
load
LW
R-type
ORi
SW
BEQ
PC lt Next(PC)
S lt A fun B
S lt A or ZX
S lt A SX
S lt A SX
0100
0110
1000
0011
1011
inc
inc
inc
inc
zero
M lt MEMS
MEMS lt B PC lt PC 4
1001
1100
inc
Rrd lt S PC lt PC 4
Rrt lt S PC lt PC 4
Rrt lt M PC lt PC 4
zero
0101
0111
1010
zero
zero
zero
31
Our Microsequencer
taken
datapath control
Z I L
Micro-PC
op-code
Map ROM
32
Microprogram Control Specification
µPC Taken Next IR PC Ops Exec Mem Write-Bac
k en sel A B Ex Sr ALU S R W M M-R Wr
Dst
  • 0000 ? inc 1
  • 0001 0 load 1 1
  • 0011 0 zero 1 0
  • 0011 1 zero 1 1
  • 0100 x inc 0 1 fun 1
  • 0101 x zero 1 0 0 1 1
  • 0110 x inc 0 0 or 1
  • 0111 x zero 1 0 0 1 0
  • 1000 x inc 1 0 add 1
  • 1001 x inc 1 0 1
  • 1010 x zero 1 0 1 1 0
  • 1011 x inc 1 0 add 1
  • 1100 x zero 1 0 0 1 0

BEQ
R
ORi
LW
SW
33
Adding the Dispatch ROM
  • Sequencer-based control unit from last lecture
  • Called microPC or µPC vs. state register
  • Control Value Effect 00 Next µaddress
    0 01 Next µaddress dispatch ROM
    10 Next µaddress µaddress 1
  • ROM

1
microPC
Adder
R-type 000000 0100 BEQ 000100 0011 ori 001101 0110
LW 100011 1000 SW 101011 1011
Mux
0
1
2
0
µAddress Select Logic
ROM
Opcode
34
Example Controlling Memory
PC
addr
InstMem_rd
Instruction Memory
IM_wait
data
Inst. Reg
IR_en
35
Controller handles non-ideal memory
instruction fetch
IR lt MEMPC
wait
wait
decode / operand fetch
A lt Rrs B lt Rrt
LW
R-type
ORi
SW
BEQ
PC lt Next(PC)
S lt A fun B
S lt A or ZX
S lt A SX
S lt A SX
M lt MEMS
MEMS lt B
wait
wait
wait
wait
Rrd lt S PC lt PC 4
Rrt lt S PC lt PC 4
Rrt lt M PC lt PC 4
PC lt PC 4
36
Overview of Control
  • Control may be designed using one of several
    initial representations. The choice of sequence
    control, and how logic is represented, can then
    be determined independently the control can then
    be implemented with one of several methods using
    a structured logic technique.
  • Initial Representation Finite State Diagram
    Microprogram
  • Sequencing Control Explicit Next State
    Microprogram counter Function Dispatch ROMs
  • Logic Representation Logic Equations Truth Tables
  • Implementation PLA ROM Technique

hardwired control
microprogrammed control
37
Microprogramming (Maurice Wilkes)
  • Control is the hard part of processor design
  • Datapath is fairly regular and well-organized
  • Memory is highly regular
  • Control is irregular and global

Microprogramming -- A Particular Strategy for
Implementing the Control Unit of a processor
by "programming" at the level of register
transfer operations Microarchitecture --
Logical structure and functional capabilities of
the hardware as seen by the
microprogrammer Historical Note IBM 360
Series first to distinguish between architecture
organization Same instruction set across wide
range of implementations, each with
different cost/performance
38
Macroinstruction Interpretation
User program plus Data this can change!
Main Memory
ADD SUB AND
. . .
one of these is mapped into one of these
DATA
execution unit
AND microsequence e.g., Fetch Calc
Operand Addr Fetch Operand(s)
Calculate Save Answer(s)
control memory
CPU
39
New Finite State Machine (FSM) Spec
IR lt MEMPC PC lt PC 4
instruction fetch
0000
decode
Q How improve to do something in state 0001?
0001
LW
BEQ
R-type
ORi
SW
ALUout lt A fun B
ALUout lt A or ZX
ALUout lt A SX
ALUout lt A SX
ALUout lt PC SX
Execute
0100
0110
1000
1011
0010
M lt MEMALUout
MEMALUout lt B
Memory
If A B then PC lt ALUout
1001
1100
0011
Rrd lt ALUout
Rrt lt ALUout
Rrt lt M
Write-back
0101
0111
1010
40
Finite State Machine (FSM) Spec
IR lt MEMPC PC lt PC 4
instruction fetch
0000
ALUout lt PC SX
decode
0001
LW
BEQ
R-type
ORi
SW
ALUout lt A fun B
ALUout lt A or ZX
ALUout lt A SX
ALUout lt A SX
If A B then PC lt ALUout
Execute
0100
0110
1000
1011
0010
M lt MEMALUout
MEMALUout lt B
Memory
1001
1100
Rrd lt ALUout
Rrt lt ALUout
Rrt lt M
Write-back
0101
0111
1010
41
Microprogramming
?-Code ROM
  • Microprogramming is a fundamental concept
  • implement an instruction set by building a very
    simple processor and interpreting the
    instructions
  • essential for very complex instructions and when
    few register transfers are possible
  • overkill when ISA matches datapath 1-1

42
Designing a Microinstruction Set
  • 1) Start with list of control signals
  • 2) Group signals together that make sense (vs.
    random) called fields
  • 3) Place fields in some logical order (e.g., ALU
    operation ALU operands first and
    microinstruction sequencing last)
  • 4) To minimize the width, encode operations that
    will never be used at the same time
  • 5) Create a symbolic legend for the
    microinstruction format, showing name of field
    values and how they set the control signals
  • Use computers to design computers

43
Again Alternative multicycle datapath (book)
  • Miminizes Hardware 1 memory, 1 adder

PCWr
PCWrCond
PCSrc
Zero
ALUSelA
MemWr
IRWr
RegWr
RegDst
IorD
1
Mux
32
PC
0
Zero
32
Rs
Ra
RAdr
5
32
32
Rt
32
Rb
busA
A
ALU
Ideal Memory
32
Reg File
5
4
Rt
0
32
Rw
WrAdr
32
B
1
32
Rd
Mem Data Reg
Din
Dout
busW
busB
2
32
3
Imm
32
ALUOp
MemtoReg
ExtOp
ALUSelB
44
12) Start with list of control signals, grouped
into fields
  • Signal name Effect when deasserted Effect when
    assertedALUSelA 1st ALU operand PC 1st ALU
    operand RegrsRegWrite None Reg. is written
    MemtoReg Reg. write data input ALU Reg. write
    data input memory RegDst Reg. dest. no.
    rt Reg. dest. no. rdMemRead None Memory at
    address is read, MDR lt MemaddrMemWrite Non
    e Memory at address is written IorD Memory
    address PC Memory address SIRWrite None IR
    lt MemoryPCWrite None PC lt PCSourcePCWriteCond
    None IF ALUzero then PC lt PCSourcePCSource
    PCSource ALU PCSource ALUoutExtOp Zero
    Extended Sign Extended

Single Bit Control
Signal name Value Effect ALUOp 00 ALU adds
01 ALU subtracts 10 ALU does function
code 11 ALU does logical OR ALUSelB 00 2nd ALU
input 4 01 2nd ALU input Regrt 10 2nd
ALU input extended,shift left 2 11 2nd ALU
input extended
Multiple Bit Control
45
34) Microinstruction Format unencoded vs.
encoded fields
  • Field Name Width Control Signals Set
  • wide narrow
  • ALU Control 4 2 ALUOp
  • SRC1 2 1 ALUSelA
  • SRC2 5 3 ALUSelB, ExtOp
  • ALU Destination 3 2 RegWrite, MemtoReg, RegDst
  • Memory 3 2 MemRead, MemWrite, IorD
  • Memory Register 1 1 IRWrite
  • PCWrite Control 3 2 PCWrite, PCWriteCond,
    PCSource
  • Sequencing 3 2 AddrCtl
  • Total width 24 15 bits

46
5) Legend of Fields and Symbolic Names
  • Field Name Values for Field Function of Field
    with Specific ValueALU Add ALU adds Subt. ALU
    subtracts Func code ALU does function
    code Or ALU does logical ORSRC1 PC 1st ALU
    input PC rs 1st ALU input RegrsSRC2 4 2nd
    ALU input 4 Extend 2nd ALU input sign ext.
    IR15-0 Extend0 2nd ALU input zero ext.
    IR15-0 Extshft 2nd ALU input sign ex., sl
    IR15-0 rt 2nd ALU input Regrtdestination r
    d ALU Regrd ALUout rt ALU Regrt ALUout
    rt Mem Regrt Mem Memory Read PC Read
    memory using PC Read ALU Read memory using
    ALUout for addr Write ALU Write memory using
    ALUout for addrMemory register IR IR MemPC
    write ALU PC ALU ALUoutCond IF ALU Zero then
    PC ALUoutSequencing Seq Go to sequential
    µinstruction Fetch Go to the first
    microinstruction Dispatch Dispatch using ROM.

47
Quick check what do these fieldnames mean?
Destination
  • Code Name RegWrite MemToReg RegDest
  • 00 --- 0 X X
  • 01 rd ALU 1 0 1
  • 10 rt ALU 1 0 0
  • 11 rt MEM 1 1 0

SRC2
Code Name ALUSelB ExtOp 000 --- X X 001 4 00
X 010 rt 01 X 011 ExtShft 10 1 100 Extend 11
1 111 Extend0 11 0
48
Specific Sequencer
  • Sequencer-based control unit
  • Called microPC or µPC vs. state register
  • Code Name Effect 00 fetch Next µaddress
    0 01 dispatch Next µaddress dispatch ROM
    10 seq Next µaddress µaddress 1
  • ROM

R-type 000000 0100 BEQ 000100 0011 ori 001101 0110
LW 100011 1000 SW 101011 1011
49
Microprogram it yourself!
  • Label ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC
    Write Sequencing
  • Fetch Add PC 4 Read PC IR ALU Seq

50
Microprogram it yourself!
  • Label ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC
    Write Sequencing
  • Fetch Add PC 4 Read PC IR ALU Seq
  • Add PC Extshft Dispatch
  • Rtype Func rs rt Seq
  • rd ALU Fetch
  • Lw Add rs Extend Seq
  • Read ALU Seq
  • rt MEM Fetch
  • Sw Add rs Extend Seq
  • Write ALU Fetch
  • Ori Or rs Extend0 Seq
  • rt ALU Fetch
  • Beq Subt. rs rt ALUoutCond. Fetch

51
Microprogramming Pros and Cons
  • Ease of design
  • Flexibility
  • Easy to adapt to changes in organization, timing,
    technology
  • Can make changes late in design cycle, or even in
    the field
  • Can implement very powerful instruction sets
    (just more control memory)
  • Generality
  • Can implement multiple instruction sets on same
    machine.
  • Can tailor instruction set to application.
  • Compatibility
  • Many organizations, same instruction set
  • Costly to implement
  • Slow

52
Summary
  • Microprogramming is a fundamental concept
  • implement an instruction set by building a very
    simple processor and interpreting the
    instructions
  • essential for very complex instructions and when
    few register transfers are possible
  • Control design reduces to Microprogramming
  • Design of a Microprogramming language
  • Start with list of control signals
  • Group signals together that make sense (vs.
    random) called fields
  • Place fields in some logical order (e.g., ALU
    operation ALU operands first and
    microinstruction sequencing last)
  • To minimize the width, encode operations that
    will never be used at the same time
  • Create a symbolic legend for the microinstruction
    format, showing name of field values and how they
    set the control signals
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