Design and Implementation of Modified Rijndael Algorithm using VHDL

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Information Engineering Technology German
University In Cairo Department of Electronics and
Electrical Engineering
A Modified Rijndael Algorithm and its
Implementation on FPGA
Ahmed Abou-Bakr Mohamed Electronics
Dept., Information Engineering Technology
German University in Cairo (GUC) Dr. Ahmed Hasan
Madian Assistant Professor, Electronics
Dept., Information Engineering Technology
German University in Cairo (GUC)
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Outline

• Introduction
• Rijndael Algorithm Implementation
• Modified Rijndael
• Implementation results
• Conclusion

Dr. Ahmed H. Madian
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Introduction

• In 1998 the DES has been expired as security
  algorithm
• National Institute of Standards and Technology
  (NIST) initiates a process to develop an Advanced
  Encryption Standard (AES)
• On November 26, 2001 NIST announced that the
  Rijndael encryption algorithm became the AES

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Rijndael

• Developed by two Belgian cryptographers where
  its based on SP-Networks.
• The ciphering process is divided into three
  stages
• Key Expansion
• Rounds
• Final Round

C. Chitu and M. Glesner, An FPGA implementation
of the AES-Rijndael in OCB/ECB modes of
operation, Microelectronics Journal 36
(2005) 139146, 21 October, 2004.
RIJNDAEL BLOCK DIAGRAM
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1- Substitution

• Its a non linear operation were 128 bit data is
  broken down into 16 chunks, 8 bits each, each of
  which is used as the address for S-box look up
  table.

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1- Substitution (contd)
Substitution Simulation
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2- Inverse Substitution
Inverse Substitution Simulation
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3- Shift Rows

• Cyclically permutes the rows of the input data to
  the left.

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3- Shift Rows (contd)
Shift Rows Simulation
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4- Inverse Shift Rows

• Cyclically permutes the rows of the input data to
  the right.

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4- Inverse Shift Rows (contd)
Inverse Shift Rows Simulation
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5- Mixing Columns
S
P

• Computes a new matrix S' by multiplying two
  matrices together the current matrix S by the
  polynomial matrix P.

2 3 1 1
1 2 3 1
1 1 2 3
3 1 1 2
S11 S12 S13 S14
S21 S22 S23 S24
S31 S32 S33 S34
S41 S42 S43 S44
S
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5- Mixing Columns (contd)

• Multiplication By 1
• The Data remains the same.
• Multiplication By 2
• The 8 bit data is left shifted by 1 bit.
• The least significant bit is replaced by 0.
• Then the most significant bit of the original
  data is used for comparison
• (a) If it is 0, then the left shifted data is
  the result.
• (b) If it is 1, then the left shifted value is
  XORed with the reduction polynomial, which in our
  case is 00011011, to generate the result.

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5- Mixing Columns (contd)
Multiplication By 2 Simulation

• Multiplication By 3
• We simply XOR the original input with the result
  of multiplication by 2.

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5- Mixing Columns (contd)
Mixing Columns Simulation
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7- Key Expansion

• One of the functions that ensures that a
  cryptography algorithm is not vulnerable.
• Generates ten matrices using the round constant
  matrix.
• The key expansion process is divided mainly into
  three operations
• Rotation
• Substitution
• Xoring

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7- Key Expansion (contd)

• Rotation
• Rotates a 32 bit input one byte to the left.
• Substitution
• Similar to the one described above.
• Xoring
• Bit wise xor operation of corresponding bits.

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7- Key Expansion (contd)

• Row 6 contains the results from xoring row 5 and
  row 2 together.
• To get row 5, row 4 is rotated, substituted and
  the xored with row 1 of the round constant
  matrix. Finally the output of such an operation
  is then xored with row 1 to get row 5.

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7- Key Expansion (contd)

• During the implementation only one matrix was
  generated, due the delay that will be caused
  since that each new row depends on the previous
  one.

Key Expansion Simulation
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8- Round Key Addition

• It simply performs a bit wise xor operation of
  the expanded round key with another input.

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8- Round Key Addition (contd)
Round Key Addition Simulation
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Modified Rijndael Algorithm
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9- Proposed Stage Of Modified Rijndael

• Mirror

• Inverse Mirror

• Doesnt require any arithmetical or logical
  operations thus routing was used during
  implementation.

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9- Proposed Stages for Rijndael Modification
(contd)
Mirror Simulation
Inverse Mirror Simulation
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10- Encryption / Decryption
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10- Encryption / Decryption (contd)
Encryption / Decryption FSM
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10- Encryption / Decryption (contd)
Encryption
Decryption
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Implementation results
Category Used Total Available Used
Slice Flip Flops 3658 18816 19
Slices 7148 9408 75
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Conclusion

• Modified Rijndeal algorithm has been presented
• The modification done with adding new stage
  mirror stage which doesnt require bigger
  hardware area.
• The system has been simulated and implemented on
  FPGA with total area of 75 and max. frequency of
  44MHz.

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• Thanks