A Non-Coherent Multi-Band IR-UWB HDR Transceiver based on Energy Detection

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• A Non-Coherent Multi-Band IR-UWB HDR Transceiver
  based on Energy Detection
• Mohamad Mroué, Sylvain Haese, Ghaïs El-Zein,
• Stéphane Mallegol and Stéphane Paquelet
• 17th IEEE International Conference on
  Electronics, Circuits and SystemsDecember 15th,
  2010Athens, Greece

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Presentation progress

• MB IR-UWB Transceiver for HDR Applications
  (Modulation Principles and Architecture)
• Analog CMOS Pulse Energy Detector (Architecture
  and Performance)
• Conclusion and Prospects

3
Presentation progress

• MB IR-UWB Transceiver for HDR Applications
  (Modulation Principles and Architecture)
• Analog CMOS Pulse Energy Detector (Architecture
  and Performance)
• Conclusion and Prospects

4
Principles of the proposed system
High data rate transmission with impulse radio ?

• Impulse radio based solution duplicated on
  multiple sub-bands
• Asynchronous treatment at reception based on
  energy detection
• Amplitude modulation On-Off Keying (OOK)
• Non-coherent demodulation energetic threshold
  comparison
• To avoid inter-symbol interference the pulse
  repetition period Tr must be greater than the
  channel delay spread Td
• Extension to multiple bands to increase the
  system capacity

(S. Paquelet et al., in joint UWBST IWUWBS, 2004)
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UWB HDR transceiver architecture

• Transmitter architecture filter bank
  implementation

Measured transmission responses versus frequency
for a 3.1-5.2 GHz octoplexer.

• Advantages of the proposed architecture
• Relaxed hardware constraints
• Only coarse synchronization is needed
• Energy based processing
• Flexibility of the multi-band architecture
• Scalable data rate / power control
• Radio resource management

n 16 to 24
Bi 250 to 500 MHz
Ti 10 to 100 ns
Tr gt 25 ns
Throughput (3 meters) gt 600 Mbps

• Receiver architecture pulse detector on each
  sub-band

• (De)multiplexer involved in the MB-OOK UWB
  transceiver
• No power division effect
• ? In-band insertion loss lt 4 dB
• No external bias (Only passive devices)
• Identical (de)multiplexer for Tx and Rx

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UWB HDR transceiver architecture

• Transceivers components
• Commercial monocycle pulse generator
• Peak-to-peak amplitude into 50 O load 3.29 V
• Duration 184 ps, center frequency 5 GHz
• Quadriplexer (3.1-4.2 GHz)
• (De)multiplexer only based on filters
• Identical (de)multiplexer for Tx and Rx
• No external bias (Only passive devices)
• No power division effect ? No need of signal
  amplification (In-band insertion loss lt 3 dB)
• Mechanical etching process using low-cost organic
  substrate (RO3010)
• Amplification stages
• Total amplification level of 42 dB
• UWB antennas
• Conical monopole (Omni-directional)
• Horn antenna (Directional with half power
  beamwidth gt 50 in the 3.1-4.2 GHz)

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Measurement results in LOS and NLOS configurations
Directional Antennas
Omni-directional Antennas
Configuration (Tx to Rx) Omni. to Omni. Omni. to Omni. Omni. to Direct. Omni. to Direct. Omni. to Direct. Direct. to Direct. Direct. to Direct. Direct. to Direct.
3-dB Bandwith 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz 250 MHz
Number of sub-bands 24 24 24 24 24 24 24 24
Range (m) 1 3 3 1 3 3 1 3
Average delay spread (ns) 17.2 34.0 34.0 9.6 16.8 16.8 8.15 11.2
Pulse repetition period (ns) 20 40 40 10 20 20 10 15
Data rate (Gbps) 1.2 0.6 0.6 2.4 1.2 1.2 2.4 1.6
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Presentation progress

• MB IR-UWB Transceiver for HDR Applications
  (Modulation Principles and Architecture)
• Analog CMOS Pulse Energy Detector (Architecture
  and Performance)
• Conclusion and Prospects

9
Implementation study of the detector

• Specifications
• Operation with large bandwidth (3.1-10.6 GHz)
• Input detector bandwidth 500 MHz
• Low mass fabrication cost
• Low power consumption and low complexity
• The circuit must provide the pulse detection on
  each sub-band

CMOS technology
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Adopted squarer circuit

• Squarer based on two MOSFETs
• When biased with zero drain to source voltage in
  the triode region
• The circuit is driven by balanced signals
• Output current
• Condition
• M1 and M2 must perfectly be matched (K, a1, a2)
• Avantages
• Simple design
• No additional power consumption
• Principle can be applied on all CMOS IC
  technologies

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Integrator

• Integrator
• Current to voltage conversion and integration
• ? directly around a capacitor
• Current amplifier
• Low input impedance square law operation of the
  first stage
• High output impedance integration and S/H stage

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Integrator

• Current amplifier
• Input bandwidth 500 MHz
• Useful part of the squared signal pass to the
  integrator unaffected
• Architecture based on current mirrors
• Easy to implement
• Reduced complexity
• Low voltage and low power consumption
• Integrator
• Output capacitor
• Current to voltage conversion
• Signal integration

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Sample and hold circuit

• Adopted architecture open loop S/H circuit
• Charge injection effects ? Sampling errors
• Charge injection compensation
• CMOS switch
• Minimum-geometry switches
• Large capacitor
• Switch architecture
• Reset switch low ON resistance rON
• Short discharge time for the hold capacitor
• Other switches minimum (W,L)
• reduce the charge injection effects
• Output stage
• Unity gain output buffer
• High input impedance

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Circuit performance

• Noise performance
• Noise level at the output of the detector
• Included detector parts squarer, current
  amplifier, switch (ON state) and the hold
  capacitor
• Estimated noise level 1 of the useful signal
  level
• Imperfection effects study
• Effect of the input impedance of the current
  amplifier on the squarer
• Gain variation of the squarer as a function of
  the input impedance
• Effects of the MOS transistors parameters
  variations
• Squarer operation
• Effect on the gain of this stage
• The square law function of the squarer is not
  affected
• Current amplifier operation Current offset and
  gain
• A modification of the architecture permit to
  reduce the generated offset current

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Pulse detector architecture

• Time domain simulation
• Simulator CADENCE Spectre
• Technology AMS 0.35 µm BiCMOS

Circuit parameters Circuit parameters Circuit parameters Circuit parameters Circuit parameters Circuit parameters Circuit parameters Circuit parameters Circuit parameters Circuit parameters
Squarer Squarer Squarer Squarer Squarer Squarer Squarer Squarer Squarer Squarer
(W/L)N (W/L)N (W/L)N 40/0.35 40/0.35 40/0.35 VG VG VG 1 V
Current amplifier Current amplifier Current amplifier Current amplifier Current amplifier Current amplifier Current amplifier Current amplifier Current amplifier Current amplifier
(W/L)N 7.2/0.35 7.2/0.35 7.2/0.35 Bandwidth at 3dB Bandwidth at 3dB Bandwidth at 3dB 563 MHz 563 MHz 563 MHz
(W/L)P 70/0.35 70/0.35 70/0.35 VDD - VSS VDD - VSS VDD - VSS 1.8 V 1.8 V 1.8 V
Ibias 84.5 µA 84.5 µA 84.5 µA Power consumption Power consumption Power consumption 0.6 mW 0.6 mW 0.6 mW
Output stage Output stage Output stage Output stage Output stage Output stage Output stage Output stage Output stage Output stage
I0 I0 240 µA 240 µA 240 µA Bandwidth at 3dB Bandwidth at 3dB Bandwidth at 3dB 825 MHz 825 MHz
VDD - VSS VDD - VSS 1.8 V 1.8 V 1.8 V Power consumption Power consumption Power consumption 1.6 mW 1.6 mW
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Pulse detector architecture

• Pulse Energy Detector with two parallel stages
  for the integrator and S/H stages.
• Time domain simulation
• Simulator CADENCE Spectre
• Technology AMS 0.35 µm BiCMOS
• Tr 15 ns, Ti 13 ns, TReset 3 ns , Ts 8 ns

Input pulse Integration Sampling Reset
1 0 1 1 0 1
Transmitted code
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Presentation progress

• MB IR-UWB Transceiver for HDR Applications
  (Modulation Principles and Architecture)
• Analog CMOS Pulse Energy Detector (Architecture
  and Performance)
• Conclusion and Prospects

18
Conclusion and prospects

• Conclusion
• Functional tests of the communicating system in
  real environment
• Comparison between the use of directional and
  Omni-directional antennas in LOS and NLOS
  configurations
• Implementation evaluation of the proposed
  Multi-band IR-UWB system
• MB IR-UWB receiver architecture

CMOS Technology
SiP approach (System in Package)
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• Thank you for your attention !

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ITE-UWB HDR Principles Performances optimal
demodulation rule
S. Paquelet, L-M. Aubert et al, UWBST 2004,  An
Impulse Radio Non-coherent Transceiver for High
Data Rates 
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ITE-UWB HDR Principles Performances/Comparisons

• Coherent - RAKE receiver
• Energy recovered on few paths
• whereas
• Quadratic integration
• Whole available energy recovered
• rake achieves comparable if it collects 33
  to 40 of the whole available energy.
• Extended Notion of OFDM
• orthogonal carrier orthogonal pulses
• intrinsic fading resistance

• CM IEEE Channel Models
• 2 NLOS 0-4 meters
• 3 NLOS 4-10 meters
• 4 Extreme NLOS multipaths

without FEC
S. Paquelet, L-M. Aubert et al, UWBST 2004,  An
Impulse Radio Non-coherent Transceiver for High
Data Rates 
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Mean performance for a given received energy when
considering the FCC limitations
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Quadriplexer (3.1-4.2 GHz)

• Mechanical etching process
• Low cost organic substrate RO3010
•  Ceramic-filled PTFE composite 
• Dielectric constant 10.2
• Metallization thickness 17 µm
• Architecture
• 1 Low pass filter
• 4 bandpass filters
• Based on resonators
• No power division effect

Sub-band (GHz) Central Frequency (Fc, GHz) Insertion loss at Fc (dB) Bandwidth at 3 dB (MHz) Bandwidth at 10 dB (MHz)
3.1-3.22 3.151 2.68 185.8 308.4
3.44-3.55 3.495 2.23 199.8 295.3
3.79-3.91 3.834 2.33 196.2 309.4
4.13-4.25 4.193 2.43 193.3 322.2
Intercept-point magnitude betweenadjacent
sub-bands gt 14 dB
(S. Mallégol et al., EuRADEuMC, 2006)
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Octoplexer (3.1-5.1 GHz)

• ANR BILBAO Project

(S. Mallégol et al., EuRADEuMC, 2006)
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Measurements and simulation results
Measurements results
Out1
3.1-5.2 GHz Octoplexer
3.1-5.2 GHz Octoplexer
3.1-5.2 GHz Octoplexer
Monocycle-pulse generator
LNA
Non-filtered monocycle pulse
Out8
Into 50 ? Vpeak-to-peak 3.29 V Duration 184
ps
CADENCE simulation results
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Modified current amplifier architecture

• Objective to reduce current offset level
  generated at the output
• Modifying the architecture of the current
  amplifier
• Altering the positions of two p-channel and
  n-channel MOS transistors
• ? Compensation of effects of MOS transistors
  parameters variations
• ? The current offset is reduced by 4 to 5 times

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Variation effects of MOS transistors parameters

• Evaluation of the current offset variation
  generated at the output of the current amplifier
• Variation of the threshold voltage VT and the
  transconductance factor K
• Comparison between analytical and simulation
  results

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Modified current amplifier architecture

• New Monte-Carlo simulation results using CADENCE
  with variations on mismatch and both mismatch and
  process parameters

mismatch
mismatch process