A Fully Integrated 4GHz Continuous-Time Bandpass ?? Converter

1
A Fully Integrated 4GHz Continuous-Time
Bandpass ?? Converter

• Q. Béraud-Sudreau, A. Mariano, D. Dallet, Y.
  Deval, J.B. Begueret
• IMS Laboratory - University of Bordeaux - France

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Outline

• Motivations
• Software Defined Radio (SDR)
• ADC Architecture
• BP ?? Modulator
• Resonator Design
• Resonator Architecture
• Simulations
• Expected performance
• Conclusion

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ADCs in Digital Receivers Towards the Software
Defined Radio
Trend ? Eliminate Downconversion, simplify the
system
Advantages Digital robustness Better
Channel Matching Frequency agility More
Degrees of Freedom
Challenges ADC needs huge dynamic range
Enormous data reduction needed in DSP
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ADCs in Digital Receivers Towards the Software
Defined Radio
Trend ? Eliminate Downconversion
Advantages Digital robustness Better
Channel Matching Frequency agility More
Degrees of Freedom
Challenges ADC needs huge dynamic range
Enormous data reduction needed in DSP
CT ?? ADC
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Continuous-Time Bandpass ?? Converter
ADC architecture for Digital Receivers
Elimination of downconversion stage Improved I
and Q matching Improved performance with
digital modulation schemes Improved flexibility
with communication standards
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Continuous-Time Bandpass ?? Converter
Digital Receiver
Ultra-Fast IC technologies
Challenges High ADC sample rates required
High ADC dynamic range required
Direct Conversion towards Software Defined Radio
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CT ?? Modulator Architecture

• DACs association (NRZ et HNRZ)
• Multi-feedback architecture
• Multi-bit quantizer
• 4th order modulator

Fin Fs/4
NRZ Non Return to Zero HNRZ Half delayed NRZ
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CT ?? Modulator Architecture

• DACs association (NRZ et HNRZ)
• Multi-feedback architecture
• Multi-bit quantizer
• 4th order modulator

Output Spectrum
Fin Fs/4
Simulation Parameters
Amplitude (dB)
Parameters Value
Input Signal 1 GHz
Modulator Bandwidth 20 MHz
Sampling Frequency 4 GHz
Modulator Resolution 3 bits
OSR Fs/2BW
SNR 87 dB _at_ 20MHz
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Continuous-time ?? Converter
Context
Non-idealities

• Need for high performance 2nd order filters
• Quality factor impact the SNR and the bandwidth
  of the modulator
• ? 2nd order resonators

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Resonator
Non-idealities

• The resonators can be implemented using LC, Gm-C,
  RC or MEMS/SAW filters.
• Integrated components have a low Q due to
  parasitic resistive losses
• A Q enhancement circuit is needed.
• Feedback loop ? Desired noise-shaping
• A transconductor will convert the voltage in
  current

? performance degradation
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Fourth-order BP ?? Modulator Topology
Context
Non-idealities
Two 2nd order resonators

• Based on transconductors (G),
• Two 2nd order resonators (L,R,C and Qt),
• A 3-bit quantizer,
• D-latches,
• Feedback DACs (NRZ and HNRZ).

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Resonator Architecture
Non-idealities
Transconductor (G)

• Fully differential structure
• Common mode rejection
• Cascode topology
• Increase the bandwidth
• Higher output resistor
• Degenerated common source
• Provide good linearity

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Resonator Architecture
Non-idealities
Resonator

• Fully differential structure
• Cross-coupled LC-tank topology

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Resonator Architecture
Non-idealities
Resonator

• Fully differential structure
• Cross-coupled LC-tank topology
• LC tank

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Resonator Architecture
Non-idealities
Resonator

• Fully differential structure
• Cross-coupled LC-tank topology
• LC tank
• Q-enhancement circuit

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Resonator Architecture
Non-idealities
Resonator

• Obtained quality factor for the 4th order filter
  (both resonators chained)
• Q 630

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Mixed Simulations
Transistor-level Circuit
VHDL-AMS Modeling
Parameters Value
Input Signal 1 GHz
Modulator Bandwidth 20 MHz
Sampling Frequency 4 GHz
Modulator Resolution 3 bits
Frequency (Hz)
SNR 70 dB _at_ 20MHz
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Mixed Simulations
Transistor-level Circuit
VHDL-AMS Modeling
Parameters Value
Input Signal 1 GHz
Modulator Bandwidth 20 MHz
Sampling Frequency 4 GHz
Modulator Resolution 3 bits
Frequency (Hz)
SNR 68 dB _at_ 30MHz
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Schematic
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CT ?? ADC Layout
DACs
Parameters Value
Input Signal 1 GHz
Sampling Frequency 4 GHz
Modulator Resolution 3 bits
Power supply 1.2V
Consumption 580mW
Size (2.21.7) mm²
Process 130nm CMOS
resonators
Quantizer DFF
LVDS Buffer
Clock buffer
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Post Layout Simulation

• Obtained output spectrum

SNR 67 dB _at_ 30MHz
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Conclusion

• Modeling and circuit design
• 2nd order resonators? CT BP ?? Modulators
• Mixed simulation
• Overall CT BP ?? Modulator
• Validate the resonators circuit design
• Post Layout Simulation
• Validate the ADC circuit design

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Thank you for your attention!
quentin.beraud-sudreau_at_ims-bordeaux.fr