EFFICIENT MODULO 2n 1 SUBTRACTORS FOR WEIGHTED OPERANDS Costas P. Efstathiou

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EFFICIENT MODULO 2n1 SUBTRACTORS FOR
WEIGHTED OPERANDS Costas P. Efstathiou

• Digital Systems and Communications Lab
• Department of Informatics
• Technological Educational Institute of Athens
• GREECE (HELLAS)

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Application of the modulo arithmetic

• Design of digital signal processors (DSP) based
  on
• residue number systems (RNS), where the
  moduli set
• 2n-1, 2n, 2n1 is extensively used.
• Correlation/convolution computation
• Cryptographic algorithms
• The efficient design of the modulo 2n1
  components
• (adders, subtractors, multipliers, ) is
  challenging since
• they operate on wider (n1)-bit operands.

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Previously proposed modulo 2n1 Subtractors

• S. Timarchi, K. Navi, M. Hosseizade, "New Design
  of RNS subtractors for modulo 2n1, in Proc. of
  2nd IEEE Int. Conf. on Information and
  Communication Technologies, 2006.
• E. Vassalos, D. Bakalis and H. T. Vergos, "Novel
  modulo 2n1 Subtractors", Proc. of the 16th Int.
  Conf. on Digital Signal Processing (DSP), 2009

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The most efficient of the previously proposed
architectures1
1E. Vassalos, D. Bakalis and H. T Vergos, "Novel
modulo 2n1 Subtractors", Proc. of the 16th Int.
Conf. on Digital Signal Processing (DSP), 2009.
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Proposed modulo 2n1 subtractor architecture
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Design Methodology
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Design Methodology (continued)
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Resulting Inverted End Around Carry Save Adder
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Simplifications for the inverted end around carry
save adder
The design of the SFA module is based on the
observation that the elements of bit pairs (an,
a0), (bn, b0) can not concurrently have the value
1
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Final stage adder
For the computation of the sum
the vectors C, S are added by an inverted
end around carry parallel adder. This adder
computes the n least significant bits of the
addition. The most significant bit is 1 when
or when CS2n-1 or
equivalently when vectors C, S are complementary.
This condition can be easily detected, in the
case of inclusive OR adders, as
, while for the case of exclusive OR adders
as Pn-11, where Gn-1, Pn-1 are the group
generate, propagate signals at the most
significant bit position of the inverted end
around adder. In Inclusive OR adders the carry
propagate signals are defined as piai?bi, while
in Exclusive OR adders as piai?bi.
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Architecture of the final stage adder
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Resulting modulo 2n1 subtractor architecture
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Comparisons

• The comparisons are based on the commonly used
  unit-gate model.
• In the unit-gate model, the 2-input gates (NAND,
  AND, etc) count as one equivalent for both area
  and delay. The XOR, XNOR gates and the 2-to-1
  multiplexer count as two equivalents.
• A full adder (FA) has area and delay complexity
  of 7 and 4 equivalents, while a half adder (HA)
  counts as 3 and 2 equivalents respectively. The
  SFA module counts as 7 and 4 gate equivalents.
• The design of the final stage adder is based on
  an exclusive-OR adder with a fast carry increment
  stage the carry computation unit of which is
  implemented according to the Ladner-Fisher
  parallel-prefix algorithm.

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Area comparison in gate equivalents
n A 1 APROP Saving
4 74 58 21.62
8 154 122 20.78
12 246 198 19.51
16 326 262 19.63
24 522 426 18.39
32 694 566 18.44
1 E. Vassalos, D. Bakalis and H. T. Vergos,
"Novel modulo 2n1 Subtractors", Proc. of
the 16th Int. Conf. on Digital Signal Processing
(DSP), 2009
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Delay comparison in gate equivalents
n T1 TPROP Saving
4 16 13 18.75
8 18 15 16.67
12 20 17 15.00
16 20 17 15.00
24 22 19 13.64
32 22 19 13.64
1 E. Vassalos, D. Bakalis and H. T. Vergos,
"Novel modulo 2n1 Subtractors", Proc. of
the 16th Int. Conf. on Digital Signal Processing
(DSP), 2009
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Area?Delay comparison
n (AxT)1 (AxT)PROP Saving
4 1184 754 36,32
8 2772 1830 33,98
12 4920 3366 31,59
16 6520 4454 31,69
24 11484 8094 29,52
32 15268 10754 29,57
1 E. Vassalos, D. Bakalis and H. T. Vergos,
"Novel modulo 2n1 Subtractors", Proc. of
the 16th Int. Conf. on Digital Signal Processing
(DSP), 2009
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Thank you!