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William Stallings Computer Organization and Architecture 7th Edition

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William Stallings Computer Organization and Architecture 7th Edition Chapter 12 CPU Structure and Function CPU Structure CPU must: Fetch instructions Interpret ... – PowerPoint PPT presentation

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Title: William Stallings Computer Organization and Architecture 7th Edition


1
William Stallings Computer Organization and
Architecture7th Edition
  • Chapter 12
  • CPU Structure and Function

2
CPU Structure
  • CPU must
  • Fetch instructions
  • Interpret instructions
  • Fetch data
  • Process data
  • Write data

3
CPU With Systems Bus
4
CPU Internal Structure
5
Registers
  • CPU must have some working space (temporary
    storage)
  • Called registers
  • Number and function vary between processor
    designs
  • One of the major design decisions
  • Top level of memory hierarchy

6
User Visible Registers
  • General Purpose
  • Data
  • Address
  • Condition Codes

7
General Purpose Registers (1)
  • May be true general purpose
  • May be restricted
  • May be used for data or addressing
  • Data
  • Accumulator
  • Addressing
  • Segment

8
General Purpose Registers (2)
  • Make them general purpose
  • Increase flexibility and programmer options
  • Increase instruction size complexity
  • Make them specialized
  • Smaller (faster) instructions
  • Less flexibility

9
How Many GP Registers?
  • Between 8 - 32
  • Fewer more memory references
  • More does not reduce memory references and takes
    up processor real estate
  • See also RISC

10
How big?
  • Large enough to hold full address
  • Large enough to hold full word
  • Often possible to combine two data registers
  • C programming
  • double int a
  • long int a

11
Condition Code Registers
  • Sets of individual bits
  • e.g. result of last operation was zero
  • Can be read (implicitly) by programs
  • e.g. Jump if zero
  • Can not (usually) be set by programs

12
Control Status Registers
  • Program Counter
  • Instruction Decoding Register
  • Memory Address Register
  • Memory Buffer Register
  • Revision what do these all do?

13
Program Status Word
  • A set of bits
  • Includes Condition Codes
  • Sign of last result
  • Zero
  • Carry
  • Equal
  • Overflow
  • Interrupt enable/disable
  • Supervisor

14
Supervisor Mode
  • Intel ring zero
  • Kernel mode
  • Allows privileged instructions to execute
  • Used by operating system
  • Not available to user programs

15
Other Registers
  • May have registers pointing to
  • Process control blocks (see O/S)
  • Interrupt Vectors (see O/S)
  • N.B. CPU design and operating system design are
    closely linked

16
Example Register Organizations
17
Instruction Cycle
  • Revision
  • Stallings Chapter 3

18
Indirect Cycle
  • May require memory access to fetch operands
  • Indirect addressing requires more memory accesses
  • Can be thought of as additional instruction
    subcycle

19
Instruction Cycle with Indirect
20
Instruction Cycle State Diagram
21
Data Flow (Instruction Fetch)
  • Depends on CPU design
  • In general
  • Fetch
  • PC contains address of next instruction
  • Address moved to MAR
  • Address placed on address bus
  • Control unit requests memory read
  • Result placed on data bus, copied to MBR, then to
    IR
  • Meanwhile PC incremented by 1

22
Data Flow (Data Fetch)
  • IR is examined
  • If indirect addressing, indirect cycle is
    performed
  • Right most N bits of MBR transferred to MAR
  • Control unit requests memory read
  • Result (address of operand) moved to MBR

23
Data Flow (Fetch Diagram)
24
Data Flow (Indirect Diagram)
25
Data Flow (Execute)
  • May take many forms
  • Depends on instruction being executed
  • May include
  • Memory read/write
  • Input/Output
  • Register transfers
  • ALU operations

26
Data Flow (Interrupt)
  • Simple
  • Predictable
  • Current PC saved to allow resumption after
    interrupt
  • Contents of PC copied to MBR
  • Special memory location (e.g. stack pointer)
    loaded to MAR
  • MBR written to memory
  • PC loaded with address of interrupt handling
    routine
  • Next instruction (first of interrupt handler) can
    be fetched

27
Data Flow (Interrupt Diagram)
28
Prefetch
  • Fetch accessing main memory
  • Execution usually does not access main memory
  • Can fetch next instruction during execution of
    current instruction
  • Called instruction prefetch

29
Improved Performance
  • But not doubled
  • Fetch usually shorter than execution
  • Prefetch more than one instruction?
  • Any jump or branch means that prefetched
    instructions are not the required instructions
  • Add more stages to improve performance

30
Pipelining
  • Fetch instruction
  • Decode instruction
  • Calculate operands (i.e. EAs)
  • Fetch operands
  • Execute instructions
  • Write result
  • Overlap these operations

31
Two Stage Instruction Pipeline
32
Timing Diagram for Instruction Pipeline Operation
33
The Effect of a Conditional Branch on Instruction
Pipeline Operation
34
Six Stage Instruction Pipeline
35
Alternative Pipeline Depiction
36
Speedup Factorswith InstructionPipelining
37
Dealing with Branches
  • Multiple Streams
  • Prefetch Branch Target
  • Loop buffer
  • Branch prediction
  • Delayed branching

38
Multiple Streams
  • Have two pipelines
  • Prefetch each branch into a separate pipeline
  • Use appropriate pipeline
  • Leads to bus register contention
  • Multiple branches lead to further pipelines being
    needed

39
Prefetch Branch Target
  • Target of branch is prefetched in addition to
    instructions following branch
  • Keep target until branch is executed
  • Used by IBM 360/91

40
Loop Buffer
  • Very fast memory
  • Maintained by fetch stage of pipeline
  • Check buffer before fetching from memory
  • Very good for small loops or jumps
  • c.f. cache
  • Used by CRAY-1

41
Loop Buffer Diagram
42
Branch Prediction (1)
  • Predict never taken
  • Assume that jump will not happen
  • Always fetch next instruction
  • 68020 VAX 11/780
  • VAX will not prefetch after branch if a page
    fault would result (O/S v CPU design)
  • Predict always taken
  • Assume that jump will happen
  • Always fetch target instruction

43
Branch Prediction (2)
  • Predict by Opcode
  • Some instructions are more likely to result in a
    jump than thers
  • Can get up to 75 success
  • Taken/Not taken switch
  • Based on previous history
  • Good for loops

44
Branch Prediction (3)
  • Delayed Branch
  • Do not take jump until you have to
  • Rearrange instructions

45
Branch Prediction Flowchart
46
Branch Prediction State Diagram
47
Dealing With Branches
48
Intel 80486 Pipelining
  • Fetch
  • From cache or external memory
  • Put in one of two 16-byte prefetch buffers
  • Fill buffer with new data as soon as old data
    consumed
  • Average 5 instructions fetched per load
  • Independent of other stages to keep buffers full
  • Decode stage 1
  • Opcode address-mode info
  • At most first 3 bytes of instruction
  • Can direct D2 stage to get rest of instruction
  • Decode stage 2
  • Expand opcode into control signals
  • Computation of complex address modes
  • Execute
  • ALU operations, cache access, register update
  • Writeback
  • Update registers flags
  • Results sent to cache bus interface write
    buffers

49
80486 Instruction Pipeline Examples
50
Pentium 4 Registers
51
EFLAGS Register
52
Control Registers
53
MMX Register Mapping
  • MMX uses several 64 bit data types
  • Use 3 bit register address fields
  • 8 registers
  • No MMX specific registers
  • Aliasing to lower 64 bits of existing floating
    point registers

54
Mapping of MMX Registers to Floating-Point
Registers
55
Pentium Interrupt Processing
  • Interrupts
  • Maskable
  • Nonmaskable
  • Exceptions
  • Processor detected
  • Programmed
  • Interrupt vector table
  • Each interrupt type assigned a number
  • Index to vector table
  • 256 32 bit interrupt vectors
  • 5 priority classes

56
PowerPC User Visible Registers
57
PowerPC Register Formats
58
Foreground Reading
  • Processor examples
  • Stallings Chapter 12
  • Manufacturer web sites specs
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