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Chapter 6b Co-simulation of chip, package and

board

- Prof. Lei He
- Electrical Engineering Department
- University of California, Los Angeles
- URL eda.ee.ucla.edu
- Email lhe_at_ee.ucla.edu

Why do We Need Co-Simulation?

- Thermal/power/electrical Coupling
- leakage power in a semiconductor device depends

on the local temperatures of individual cells - temperature distributions also depend on leakage

power distributions - temperature dependence of a metals electrical

conductivity - Joule heating (or self-heating) of metals with

currents flowing through - Integrated RDL, package, and board model
- Increasingly, package and system designers have

started to include RDL traces in package models

because in todays designs RDL and package traces

are so close to each other that coupling between

them is significant.

2

3

Importance of Co-Simulation

- A differential pair from chip to package to board

Comparison of s-parameter results between

segregated and integrated models Figures

obtained from An-Yu Kuo, Apache Design Solutions

4

Chip/Package/Board Modeling

- It is impossible to put detailed models of chip,

package and board together for the simulation due

to the high complexity - We need some simplified models that preserve only

necessary information for the simulation - But how?

Outline

- Chip Modeling
- Current Source Model
- SPICE Transistor Model
- IBIS (I/O Buffer )
- CMP Model
- Package and Board Modeling
- S Parameters

Current Source Model

- Traditional current source model for the chip
- the non-linearity of the I/O buffer is ignored gt

negative feedback effect is ignored

SPICE Transistor Models

- SPICE simulations model a circuit at transistor

level - SPICE models contain detailed information about

the circuit and process parameters which is

regarded as proprietary - IC vendors are reluctant to provide..
- Not all SPICE simulators are fully compatible.
- Slow simulation speed.
- SPICE has various simulator options that control

accuracy, convergence and the algorithm type - Any options that are not consistent might give

rise to poor correlation in simulation results

across different simulators

- IBIS, is an alternative to SPICE simulation
- esp. when we are interested in its I/O behavior

What Is IBIS?

- I I/O
- B Buffer
- I Information
- S Specification
- IBIS is a universal standard for describing the

analog behavior of digital device buffers using

data in ASCII text format - Started in the early 90s to promote

tool-independent I/O models for system-level

signal integrity work - IBIS 3.2 is standardized ANSI/EIA-656-A and IEC

62014-1 - IBIS 4.1 incorporates links to VHDL-AMS and

Verilog-AMS

http//www.eigroup.org/ibis/ http//www.ibis-infor

mation.org/

IBIS files are not really models, they just

contain the data that will be used by the

simulation tools behavioral models and algorithms

Simulation Models IBIS

- IBIS behavioral data is taken from actual

devices. - IBIS models tend to simulate much faster than

SPICE models. - IBIS Modeling provides a simple table-based

buffer model for semiconductor devices. - IBIS models can be used to characterize I/V

output curves, rising/falling transition

waveforms, and package parasitic information of

the device. - IBIS models are intended to provide

nonproprietary information about I/O buffers and

are more easily available from different IC

vendors - Non-convergence is eliminated in IBIS simulation.

- Virtually all EDA vendors presently support IBIS

models, and ease of use of these IBIS simulators

is generally very good. - IBIS models for most devices are freely available

over the Internet making it easy to simulate

several different manufacturers devices on the

same board.

Elements of an IBIS Model

2

3

4

5

1

Elements of an IBIS Model

- Element 1 Pull-down
- Describes the I/V characteristics during

pull-down. - Data for minimum and maximum current for given

voltages. - Data is taken for -Vcc to 2Vcc as that allows a

behavioral model for signal reflections caused by

improper termination and overshoot and undershoot

situations when the protection diodes are

forward biased.

Element 1

Elements of an IBIS Model

- Element 2 Pull-up
- Describes the pull-up state of the buffer when

the output drives high. - Data is entered using the formula Vtable Vcc

Voutput - The minimum and maximum values are determined by

the minimum and maximum operating temperatures,

supply voltages and process variations. - Combining the highest current values with the

fastest ramp time and minimum package

characteristics, a fast model can be derived. A

slow model can be derived by combining the lowest

current with the slowest ramp time and maximum

package characteristics.

Element 2

Elements of an IBIS Model

- Element 3 GND and Power Clamps
- Describes the ground and power clamp diodes.
- The GND clamp curve is derived from the ground

relative data gathered while the buffer is in the

high-impedance state and illustrates the region

where the ground clamp diode is active. The range

is from -Vcc to Vcc. - The power clamp curve is derived from the Vcc

relative data gathered while the buffer is in a

high impedance state and shows the region where

the power clamp diode is active. This measurement

ranges from Vcc to 2Vcc.

Element 3

Elements of an IBIS Model

- Element 4 Ramp
- Describes the ramp time for the pull-up and

pull-down devices. Ensures proper AC operation of

the model. - The min and max columns represent the minimum and

maximum slew rates for the buffers. - The values represent the intrinsic values of the

transistors with all package parasitics and

external loads removed.

Element 4

Elements of an IBIS Model

- Element 5 Package
- Adds the component and package parasitics.
- C_comp is the capacitance of the die itself,

excluding the package capacitance. - Package characteristic resistance, inductance and

capacitance are added by R_pkg, L_pkg, and C_pkg,

respectively.

Element 5

16

Putting it all together the IBIS File

- A standard IBIS model file consists of three

sections - Header Info
- basic information about the IBIS file and what

data it provides. - Component, Package, and Pin Info
- the targeted device package, pin lists, pin

operating conditions, and pin-to-buffer mapping. - V-I Behavioral Model
- all data to recreate I-V curves as well as V-t

transition waveforms, which describe the

switching properties of the particular buffer.

Chip Power Network Model

- Traditional model
- This simplified model of the dies power delivery

network can result in inaccurate global power

analysis - die current can influence the voltage drop

through the system - the resistive and capacitive components of the

die can determine the resonance frequency and its

amplitude.

18

Chip Power Network Model

- CPM Model from Apache
- CPM contains current sources and R, L, and C

parasitics. - It provides a reduced view of effective Rdie and

Cdie for different frequencies of operation. - It also provides switching current that varies

over time and space

19

Organization

- Chip Modeling
- IBIS
- CPM
- Package and Board Modeling
- S Parameters and Co-simulation Flow

Black Box Representation

- S-parameters are a useful method for

representing a circuit as a black box - The external behaviour of this black box can be

predicted without any regard for the contents of

the black box. - a resistor
- a transmission line
- an integrated circuit.

Definition of Ports

A black box or network may have any number of

ports.

This diagram shows a simple network with just 2

ports.

Note A port is a terminal pair of lines.

S Parameter Definition

S-parameters are measured by sending a single

frequency signal into the network or black box

and detecting what waves exit from each port.

Power, voltage and current can be considered to

be in the form of waves travelling in both

directions. For a wave incident on Port

1, some part of this signal reflects back out of

that port and some portion of the signal exits

other ports.

Explanation of S Parameters

For a two-port system

First lets look at S11. S11 refers to the

signal reflected at Port 1 for the signal

incident at Port 1. Scattering parameter S11 is

the ratio of the two waves b1/a1.

Explanation of S Parameters

For a two-port system

Now lets look at S21. S21 refers to the

signal exiting at Port 2 for the signal incident

at Port 1. Scattering parameter S21 is the ratio

of the two waves b2/a1.

Explanation of S Parameters

For a two-port system

Now lets look at S21. S21 refers to the

signal exiting at Port 2 for the signal incident

at Port 1. Scattering parameter S21 is the ratio

of the two waves b2/a1.

S21? Surely that should be S12?? S21 is correct!

S-parameter convention always refers to the

responding port first!

Explanation of S Parameters

Explanation of S Parameters

A linear network can be characterised by a set of

simultaneous equations describing the exiting

waves from each port in terms of incident

waves. S11 b1 / a1 S12 b1 / a2 S21

b2 / a1 S22 b2 / a2 Note again how the

subscript follows the parameters in the ratio

(S11b1/a1, etc...)

Explanation of S Parameters

Explanation of S Parameters

S-parameters are complex (i.e. they have

magnitude and angle) because both the magnitude

and phase of the input signal are changed by the

network. (This is why they are sometimes

referred to as complex scattering parameters).

These four S-parameters actually contain eight

separate numbers the real and imaginary parts

(or the modulus and the phase angle) of each of

the four complex scattering parameters. Quite

often we refer to the magnitude only as it is of

the most interest. How much gain (or loss) you

get is usually more important than how much the

signal has been phase shifted.

What do S-parameters depend on?

S-parameters depend upon the network and the

characteristic impedances of the source and load

used to measure it, and the frequency measured

at. i.e. if the network is changed, the

S-parameters change. if the frequency is

changed, the S-parameters change. if the load

impedance is changed, the S-parameters

change. if the source impedance is changed, the

S-parameters change.

In the Si9000e S-parameters are quoted with

source and load impedances of 50 Ohms

A little math

This is the matrix algebraic representation of 2

port S-parameters

Some matrices are symmetrical. A symmetrical

matrix has symmetry about the leading diagonal.

In the case of a 2-port network, that means

that S21 S12 and interchanging the input and

output ports does not change the transmission

properties. A transmission line is an example of

a symmetrical 2-port network.

- Parameters along the leading diagonal, S11

S22, of the S-matrix are referred to as

reflection coefficients because they refer to the

reflection occurring at one port only. - Off-diagonal S-parameters, S12, S21, are

referred to as transmission coefficients because

they refer to what happens from one port to

another.

How about Larger networks

- A Network may have any number of ports ...
- The S-matrix for an n-port network contains n2

coefficients (S-parameters), each one

representing a possible input-output path. - The number of rows and columns in an

S-parameters matrix is equal to the number of

ports. - For the S-parameter subscripts ij, j is the

port that is excited (the input port) and i is

the output port.

Yes i for output j for input logical -)

(No Transcript)

Sum up

- S-parameters are a powerful way to describe an

electrical network - S-parameters change with frequency / load

impedance / source impedance / network - S11 is the reflection coefficient
- S21 describes the forward transmission

coefficient (responding port 1st!) - S-parameters have both magnitude and phase

information - Sometimes the gain (or loss) is more important

than the phase shift and the phase information

may be ignored - S-parameters may describe large and complex

networks

Co-Simulation Flow

Frequency domain

CPM/IBIS model in s domain for circuits

Time domain

CPM/IBIS model for circuits

S parameters for package/board

Ckt realization of S parameters for

package/board

IFFT

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Simulation of S-Parameters

- S-parameter models can be simulated directly

using convolution based methods. - It is also possible to synthesize an RLC circuit

from S-parameters - for a given S-parameter there are an infinite

number of circuits that can correspond to it. - general approach
- create a circuit template with a certain topology
- convert the measured S parameters to Y or Z

parameters - by matching the Y/Z parameters of the template

and the measured Y/Z parameters (e.g. matching

their poles and zeros), we can determine the

element values in the template

References

- S. Emami, C. H. Doan, A. M. Niknejad, R. W.

Brodersen, Large-signal millimeter-wave CMOS

modeling with BSIM3," RFIC Digest of Papers, pp.

163-166, June 2004. - C. H. Doan, S. Emami,A. M. Niknejad,

andR.W.Brodersen, Millimeter-wave CMOS design,

IEEE Journal of Solid-State Circuits, vol. 40,

pp. 144-155, Jan. 2005. - M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J.

G. Versleijen, An improved de-embedding

technique for on-wafer high-frequency

characterization, in Proc. IEEE Bipolar/BiCMOS

Circuits and Technology Meeting, Sep. 1991, pp.

188191. - Dr. Jan Verspecht (December 2005). "Large-Signal

Network Analysis, IEEE Microwave Magazine (IEEE)

6 (4) 8292.

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