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Models for Delay, Signal Integrity and Power integrity

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Title: Models for Delay, Signal Integrity and Power integrity Author: Yiyu Last modified by: User Created Date: 8/29/2010 4:04:36 PM Document presentation format – PowerPoint PPT presentation

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Title: Models for Delay, Signal Integrity and Power integrity


1
Chapter 2Interconnect AnalysisDelay Modeling
Prof. Lei He Electrical Engineering
Department University of California, Los
Angeles URL eda.ee.ucla.edu Email
lhe_at_ee.ucla.edu
2
Outline
  • Delay models
  • RC tree Elmore delay (First Order)
  • Second Order Analysis (S2P algorithm)
  • Gate delay

3
Input-to-Output Propagation Delay
  • The circuit delay in VLSI circuits consists of
    two components
  • The 50 propagation delay of the driving gates
    (known as the gate delay)
  • The delay of electrical signals through the wires
    (known as the interconnect delay)

4
Lumped vs Distributed Interconnect Model
Lumped
Distributed
How to analyze the delay for each model?
5
Lumped RC Model
  • Impulse response and step response of a lumped
    RC circuit

6
Analysis of Lumped RC Model
S-domain ckt equation (current equation)
Frequency domain response for step-input
Frequency domain response for impulse
match initial state
Time domain response for step-input
Time domain response for impulse
7
50 Delay for lumped RC model
1
0.5
50 delay
How about more complex circuits?
8
Distributed RC-Tree
  • The network has a single input node
  • All capacitors between node and ground
  • The network does not contain any resistive loop

9
RC-tree Property
  • Unique resistive path between the source node s
    and any other node i of the network ? path
    resistance Rii
  • Example R44R1R3R4

10
RC-tree Property
  • Extended to shared path resistance Rik
  • Example Ri4R1R3
  • Ri2R1

11
Elmore Delay
  • Assuming
  • Each node is initially discharged to ground
  • A step input is applied at time t0 at node s
  • The Elmore delay at node i is
  • Theorem The Elmore delay is equivalent to the
    first-order time constant of the network
  • Proven acceptable approximation of the real delay
  • Powerful mechanism for a quick estimate

12
Example
  • Elmore delay at node i is

13
Interpretation of Elmore Delay
  • Definition
  • h(t) impulse response
  • TD mean of h(t)
  • Interpretation
  • H(t) output response (step process)
  • h(t) rate of change of H(t)
  • T50 median of h(t)
  • Elmore delay approximates the median of h(t) by
    the mean of h(t)

14
Elmore Delay Approximation
15
RC-chain (or ladder)
  • Special case
  • Shared-path resistance ?path resistance?

16
RC-Chain Delay
VN
Vin
Rr L/N CcL/N
  • Delay of wire is quadratic function of its length
  • Delay of distributed rc-line is half of lumped RC

17
Outline
  • Delay models
  • RC tree Elmore delay (First Order)
  • Second Order Analysis (S2P algorithm)
  • Gate delay

18
Stable 2-Pole RC delay calculation (S2P)
  • The Elmore delay is the metric of choice for
    performance-driven design applications due to its
    simple, explicit form and ease with which
    sensitivity information can be calculated
  • However, for deep submicron technologies
    (DSM), the accuracy of the Elmore delay is
    insufficient

19
Moments of H(s)
  • Moments of H(s) are coefficients of the Taylors
    Expansion of H(s) about s0

20
Driving Point Admittance
  • Let Y(s) be an driving point admittance
    function of a general RC circuit. Consider its
    representation in terms poles and residues

where q is the exact order of the circuit
Moments of Y(s) can be written as
21
S2P Algorithm
  • Compute m1, m2, m3 and m4 for Y(s)
  • Find the two poles at the driving point
    admittance as follows
  • To match the voltage moments at the response
    nodes, choose
  • and the S2P approximation is then expressed as

Note that m0 and m1 are the moments of H(s).
m0 is the Elmore delay.
22
S2P Vs. Elmore Delay
23
Outline
  • Delay models
  • RC tree Elmore delay (First Order)
  • Second Order Analysis (S2P algorithm)
  • Gate delay

24
Gate Delay and Output Transition Time
  • The gate delay and the output transition time
    are functions of both input slew and the output
    load

25
General Model of a Gate
26
Definitions
27
Output Response for Different Loads
28
Output Transition Time
  • Output transition time as a function of input
    transition time and output load

29
ASIC Cell Delay Model
  • Three approaches for gate propagation delay
    computation are based on
  • Delay look-up tables
  • K-factor approximation
  • Effective capacitance
  • Delay look-up table is currently in wide use
    especially in the ASIC design flow
  • Effective capacitance promises to be more
    accurate when the load is not purely capacitive

30
Table Look-Up Method
  • What is the delay when Cload is 505f F and Tin is
    90pS?

31
K-factor Approximation
  • We can fit the output transition time v.s.
    input transition time and output load as a
    polynomial function, e.g.
  • A similar equation gives the gate delay

32
One Dimensional Table
Linear model
33
Two Dimensional Table
Quadratic model
34
Second-order RC-p Model
  • Using Taylor Expansion around s 0

35
Second-order RC-p Model (Contd)
  • This equation requires creation of a
    four-dimensional table to achieve high accuracy
  • This is however costly in terms of memory space
    and computational requirements

36
Effective Capacitance Approach
  • The Effective Capacitance approach attempts
    to find a single capacitance value that can be
    replaced instead of the RC-p load such that both
    circuits behave similarly during transition

37
Output Response for Effective Capacitance
38
Effective Capacitance (Contd)
39
Effective Capacitance (Contd)
0ltklt1
  • Because of the shielding effect of the
    interconnect resistance , the driver will only
    see a portion of the far-end capacitance C2

40
Effective Capacitance for Different Resistive
Shielding
41
Macys Approach
  • Assumption If two circuits have the same
    loads and output transition times, then their
    effective capacitances are the same
  • gt the effective capacitance is only a function
    of the output transition time and the load

42
Macys Iterative Solution
  1. Compute a from C1 and C2
  2. Choose an initial value for Ceff
  3. Compute Tout for the given Ceff and Tin
  4. Compute b
  5. Compute g from a and b
  6. Find new Ceff
  7. Go to step 3 until Ceff converges

43
Summary
  • Delay model
  • Elmore delay
  • Gate delay look-up table, k-factor
    approximation, effective capacitance

43
44
References
  • R. Macys and S. McCormick, A New Algorithm for
    Computing the Effective Capacitance in Deep
    Sub-micron Circuits, Custom Integrated Circuits
    Conference 1998, pp. 313-316
  • J. Qian, S. Pullela, and L. T. Pileggi, "Modeling
    the "effective capacitance" for the RC
    interconnect of CMOS gates," IEEE Trans. on
    Computer-Aided Design of Integrated Circuits and
    Systems, vol. 13, pp. 1526-1535, Dec. 1994.
  • Jason Cong , Lei He , Cheng-Kok Koh , Patrick H.
    Madden, Performance optimization of VLSI
    interconnect layout, Integration, the VLSI
    Journal, v.21 n.1-2, p.1-94, Nov. 1996 (Section
    2.1-2.2)
  • W. C. Elmore, The Transient Response of Damped
    Linear Networks with Particular Regard to
    Wideband Amplifiers, Journal of Applied Physics,
    1948.
  • Jorge Rubinstein, and etc. Signal Delay in RC
    Tree Networks, TCAD'83
  • Emrah Acar, Altan Odabasioglu, Mustafa Celik, and
    Lawrence T. Pileggi. 1999. S2P A Stable 2-Pole
    RC Delay and Coupling Noise Metric.
    In Proceedings of the Ninth Great Lakes Symposium
    on VLSI(GLS '99).

44
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