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PPT – CSE241A: Introduction to Computing Circuitry (ECE260B: VLSI Integrated Circuits and Systems Design) Winter 2003 Lecture 01: Introduction PowerPoint presentation | free to download - id: 5d1b64-NDU4Z

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CSE241A Introduction to Computing

Circuitry(ECE260B VLSI Integrated Circuits and

Systems Design)Winter 2003Lecture 01

Introduction

Outline

- Introduction
- Motivation/Trends
- Transistor
- Basic logic blocks
- Performance
- Power

Logistics

- Instructor Andrew B. Kahng (UCSD CSE ECE)
- abk_at_cs.ucsd.edu
- TA Benjamin Cichy (on UCSD CSE staff)
- cichy_at_vlsicad.ucsd.edu
- Class Tu, Th 930am-1050am, Center 217B
- Recitation Wed 200-300pm
- Lab Wed 330-500pm EBU1 3327
- Text M. J. S. Smith, Application-Specific

Integrated Circuits, Addison-Wesley, 1997.

Chapters 1-3, 11-17 - Website vlsicad.ucsd.edu/courses/cse241a

Class Info

- CSE241A and ECE260B crosslisted
- Prerequisites
- ECE 260B ECE 260A
- CSE 241A CSE 240
- 6 labs, 1 project (through quarter), 19

lectures - Meeting 5 guest lecture (synthesis)
- Meeting 8 midterm
- Grading
- 40 project, 25 midterm, 20 homework, 15 lab
- Content CMOS devices and manufacturing

technology. CMOS logic gates and their layout.

Propagation delay, noise margins, and power

dissipation. Combinational (e.g., arithmetic)

and sequential circuit design. Memory design.

Overall ASIC implementation flow.

Other Notes

- Check website frequently for new slides or other

updates - This course will be under construction

throughout the quarter expect small resets as we

go - My background CS, and VLSI CAD (physical

design, back-end implementation methodology,

performance analysis, design-manufacturing

interface) - Homework
- Due, neatly written or printed, at the end of

class one week after the question appears in

lecture slides - No extensions unless a doctors note is provided
- Academic integrity
- All work must be your own unless collaboration is

specifically permitted - All sources must be specifically and completely

acknowledged - Violations will be reported per university

regulations

Class Objectives

- Learn about ASIC implementation flow

Verilog?GDSII - Design and implementation of CMOS digital

circuits, and optimization with respect to

different constraints cost, area, speed, power

dissipation, and reliability - High-level overview of each phase of the design

flow - Introduce industry-standard design tools
- Logic synthesis Synopsys Design Compiler
- Place and route Cadence Silicon Ensemble

(SE-PKS) - Physical verification Cadence Assura / Diva
- Prepare for future design experiences
- Synthesize a modern processor (soft core) into

GDSII

Other Objectives

- Understand basic building blocks of VLSI
- Transistors and wires
- Logic gates and other (memory, datapath) blocks
- Layout
- Conceptually model and build system
- State-machine design (RTL)
- Verilog modeling
- Synthesis, place and route
- Understand constraints and tradeoffs
- Timing (gates and interconnects)
- Clocking methodology
- System integration issues (power/ground routing,

noise, package, cost) - Note You should have taken logic design (Boolean

logic, K-maps, state machines), and some ECE 165

(UG VLSI) background as well - We will review or develop quickly basic circuit

theory (MOS device parasitics, performance)

Verilog HDL EDA tools (layout, schematic

capture, simulation/synthesis) logic design

(minimization, FSMs)

Outline

- Introduction
- Motivation/Trends
- Transistor
- Basic logic blocks
- Performance
- Power

Cost and Integration Drivers

- Moores Law is about cost
- How many distinct statements (versions) of

Moores Law can you find? - Increased integration, decreased cost ? more

possibilities for semiconductor-based products - Pentium 4 die shot
- Estimate (a) the number of SRAM bitcells per

square millimeter, and (b) the number of logic

gates per square millimeter, in 130nm CMOS.

2.2cm

Slide courtesy of Mary Jane Irwin, PSU

MOS Transistor Scaling (1974 to present)

- Homework Q1 (a) What is the website of the

International Technology Roadmap for

Semiconductors (ITRS)? (b) How many chapters

are in the ITRS? (c) How is transistor

performance (speed) measured in the ITRS, and

what is the predicted speed of a high-performance

transistor in the 65nm node?

Source 2001 ITRS - Exec. Summary, ORTC Figure

Half Pitch ( Pitch/2) Definition

Source 2001 ITRS - Exec. Summary, ORTC Figure

Sense of Scale (Scaling)

- What fits on a VLSI Chip today?
- State of the art logic chip
- 20mm on a side (400mm2)
- 0.13mm drawn gate length
- 0.5mm wire pitch
- 8-level metal
- For comparison
- 32b RISC processor
- 8K l x 16Kl
- SRAM
- about 32l x 32l per bit
- 8K x 16K is 128Kb, 16KB
- DRAM
- 8l x 16l per bit
- 8K x16K is 1Mb, 128KB

0.13mm (2 l)

0.5mm (8 l)

64b FP Processor

20mm (40,000 wire pitches) 320,000 l

32b RISC Processor

Slide courtesy of Ken Yang, UCLA

Design Levels

- Specification
- what the system (or component) is supposed to do
- Architecture
- high-level design of component
- state defined
- logic partitioned into major blocks
- Logic
- gates, flip-flops, and the connections between

them

- Circuit
- transistor circuits to realize logic elements
- Device
- behavior of individual circuit elements
- Layout
- geometry used to define and connect circuit

elements - Process
- steps used to define circuit elements

Can describe design at many different levels of

abstraction

Slide courtesy of Mary Jane Irwin, PSU

Abstractions and Disciplines

- Digital abstraction
- signals are 1 or 0
- Switch abstraction
- MOSFETs as simple switches
- Gate abstraction
- Unidirectional elements
- Separable timing
- Synchronous abstraction
- Race free logic
- Function does not depend on timing

- Constrain the design space to simplify the design

process - Balance between design complexity and performance
- E.g., standard-cell methodology
- Orthogonalize concerns
- Architecture and implementation
- Logic and timing
- Logic and embedding
- Partition the problem (hierarchy)
- Module is a box with pins
- Apply recursively

Slide courtesy of Mary Jane Irwin, PSU

Design Procedure and Tools

- Concept
- divider
- Architecture
- subtract/compare
- Logical Implementation
- abbcac
- xor
- Circuit Implementation
- transistors
- Physical layout Verify
- mask layers (rectangles)

- C-modeling
- Behavior modeling
- Verilog or VHDL
- Logic synthesis
- Design Compiler (Synopsys)
- Verification of synthesis
- Static timing analysis
- Place and route
- Silicon Ensemble (Cadence)
- Verification of layout
- Dynamic timing analysis

- Exercise (a) List the top 6 Electronic Design

Automation (EDA) companies according to annual

revenue. (b) Estimate the percentage of EDA

industry revenue garnered by the remaining (how

many?) companies in the industry, and explain how

you reached this estimate.

Slide courtesy of Mary Jane Irwin, PSU

Bigger Picture of Design Flow

Standard Cell Library

Wire Model

Device model

Schematic Entry

r,s, m

3-D RLC Modeling Tool

Cell Characterization

Layers

Layout Entry

Layout rules

Synthesis Library (Timing/Power/Area)

Parasitic Extraction Library

Place Route Library (Ports)

C-Model

Verilog Behavioral Model

Structural Model

Global Layout

Block Layout

Synthesis

P R

Verilog Structural RTL

Floorplan

Floorplan

P R

DRC/ERC/LVS

Static/Dynamic Timing w/extract

Functional

Functional

Power/Area

Scan/Testability

Static Timing

Clock Routing/Analysis

Slide courtesy of Mary Jane Irwin, PSU

Outline

- Introduction
- Motivation/Trends
- Transistors
- Basic logic blocks
- Performance
- Power

NMOS Transistors

poly

n

n

p

channel

- Raising the gate voltage attracts electrons to

form a thin n-region under the gate, called

the channel, through which current flows between

the two n regions - If the n-channel is not present, the two n

regions are separated by back-to-back diodes,

which blocks current flow - The gate voltage at which a channel forms depends

on the value of VGS VG-VS - The gate must first repel away the positive

charge before building up the negative channel - For this to happen requires VGS gt VT, where VT is

the threshold voltage - (When VGS lt VT , subthreshold current is still

flowing)

Slide courtesy of Ken Yang, UCLA

MOSFET as Switch

- (NMOS) three-terminal device
- Source, Drain
- two ends of conductive path
- VDS (voltage of drain with respect to source)

must be positive for current to flow - Gate
- controls conductive path
- Operation
- conducts (on) when gate is high (1)
- open circuit (off) when gate is low (0)
- Passes 0s well, but not 1s Why?

source

drain

gate

For PMOS, everything is reversed source

terminal must have higher voltage, and the

transistor is on when the gate is much lower than

the source

Transistor Operation

- Voltage on gate induces a charge in the channel
- Voltage across source-drain creates a field that

moves the charge (Source is the lower voltage for

an nMOS) - IDS Qper_length velcarrier
- Vel m EDS
- m is electron mobility
- COXTOT Cox A eoxA/tox

Qper_length COXTOT/L(VGS-VT)

COXTOT/LVGT

W

Gate

Source

Drain

EDS

Well/Substrate

L

- Slide courtesy of Ken Yang, UCLA

Resistive Region

- At low VDS (and large VGS-VT), channel voltage is

essentially constant and charge remains uniform

across channel - Device acts as a resistor
- EDS VDS/L
- IDS KVGTVDS
- Where K mCoxW/L

QpL WCOX(VGS-VT) WCOXVGT

Gate

Source

Drain

- Slide courtesy of Ken Yang, UCLA

Linear/Triode Region

- If we raise VDS so that the charge under the gate

near the drain differs from that near the source. - Take the average Qper_ length

Gate

Source

Drain

Ave(QpL) ½(WCOX(VGS-VT) WCOX(VGD-VT))

WCOX(VGT-VDS/2)

- Slide courtesy of Ken Yang, UCLA

Current-Source (Saturation) Region

- At high VDS gt VGT, channel voltage, and hence

charge slopes across channel - Charge pinches off near drain
- The drain voltage no longer affects channel
- With the VGS fixed, the device acts as a current

source.

Gate

VD gt VG-VT

Source

Drain

V_at_pinchoff VG-VT

- Slide courtesy of Ken Yang, UCLA

Transistor Summary

- Three regions of operation
- Off (VGSltVT)
- Triode/Linear (VGDgtVT)
- Saturated (VGSgtVT and VGDltVT or VGDgtVGS-VT)
- The value of the current is proportional to the

gate to source voltage minus threshold voltage,

VGS-VT - Current inversely proportional to the oxide

thickness - Current proportional to width (width of the

diffusion), inversely proportional to length

(width of the poly) - So
- Resistance of transistor is proportional to

length and inversely proportional to width

- Slide courtesy of Ken Yang, UCLA

MOS Approximation

- The transistors resistance is variable and

depends on the gate voltage. - This approximation is ok for timing estimates,

but not for analog circuits

- Slide courtesy of Ken Yang, UCLA

Complementary Transistors

c

f

e

a

b

d

f low ? d connected to e

c high ? a connected to b

- PMOS transistors have negative threshold voltage
- Devices turn on when gate is LOWER than source by

more than threshold voltage - Source is the diffusion terminal with the HIGHER

voltage - Draw bubble or o on gate of PMOS device
- Complementary device types
- NMOS connected when gate is high
- Passes 0, but high output is degraded
- PMOS connected when gate is low
- Passes 1, but low output is degraded

Switch Networks

- Since transistors can be modeled as switches
- Draw an abstract switch as
- Control (gate) terminal is on top
- We can build switch networks between two

non-control terminals - Define the function of a switch network by the

conditions on inputs that will connect the two

terminals of the network - Structure of switch network sets its logic

functions - OR functions are constructed by parallel

switches - AND function are constructed by series switches
- VLSI chip millions of these switch networks

A

X

Y

A

B

X

Y

Outline

- Introduction
- Motivation/Trends
- Transistors
- Basic logic blocks
- Performance
- Power

NOR Gate

- F(NOR) (AB)
- Output is low when either A or B is high.
- NMOSs form an OR network to VGND.
- Output is high when A and B are both low
- PMOSs form an AND network to VDD.

NOR Output

- Slide courtesy of Ken Yang, UCLA

NAND Gate

- NAND
- Output is low when A and B are both high
- Output is high when either A or B is low

NAND Output

- Slide courtesy of Ken Yang, UCLA

Static CMOS Logic Family

- Can implement any function
- To build a logic gate g(x1, , xn) f(x1, ,

xn) , need to build two switch networks - Pull-down a(x1, , xn) f(x1, , xn)
- Pull-up b(x1, , xn) f(x1, , xn)

- Note PMOS inverts inputs

PMOS pull-up network Connects the output to VDD

when f is FALSE

PMOS only, since only passes 1

NMOS pull-down network Connects the output to

VGND when f is TRUE

NMOS only, since only passes 0

- Slide courtesy of Ken Yang, UCLA

Duality

- Pull-up and pull-down networks are duals of each

other - Dual of a function
- Exchange ANDs and ORs
- Example Duals
- A B A B
- (A B ) C (A B) C
- For switch networks
- AND series switches
- OR parallel switches
- So
- Parallel pull-down, serial pull-up and vice versa

- Slide courtesy of Ken Yang, UCLA

De Morgans Law

- (a b) a b
- (a b) a b
- Complement of a function is obtained by replacing

each variable / element with its complement, and

exchanging the AND and OR operations - If element is not a single variable, then apply

recursively to the expressions - ((AB) C) (A B) C (A B) C
- ((A B) (C D)) (A B) (C D) (A B)

(C D)

- Slide courtesy of Ken Yang, UCLA

Complex Gate Example

- Function And-Or-Invert (AOI) g(ABC)
- Pull-down implements fN ABC
- Pull-up implements DUAL of fN
- fP (AB)C - inverted inputs
- The network that you build is (AB)C

invert

or

and

- Slide courtesy of Ken Yang, UCLA

More Examples

- 3 input function, g a(bc) bc
- For pull-down, f (abc)(bc)
- For pull-up, f a(bc)bc
- 5 input function, g ab (cde)
- For pull-down, f (ab)(cde)
- For pull-up, f ab (c d e)
- Depth of stacking is approximately the number of

inputs ? performance

implications

- Homework Q2 Draw the transistor schematic for

(a) a 3-input XOR gate, and (b) g a(cd b)

bc

- Slide courtesy of Ken Yang, UCLA

Outline

- Introduction
- Motivation/Trends
- Transistors
- Basic logic blocks
- Performance
- Power

Circuit Performance Estimation

Deep Sub-micron (DSM) MOSFET models

- Slide courtesy of Kevin Cao, Berkeley

Reverse Scaling of Global Interconnects

Passivation

Dielectric

Wire

Etch Stop Layer

Via

Global (up to 5)

Dielectric Capping Layer

Copper Conductor with Barrier/Nucleation Layer

Intermediate (up to 4)

Local (2)

Pre Metal Dielectric

Tungsten Contact Plug

- What are some implications?

- Slide courtesy of Chris Case, BOC Edwards

Interconnect Statistics

- What are some implications?

Acceleration of Gate Length Scaling

- What are some implications?

- Slide courtesy of Numerical Technologies, Inc.

Crosstalk From Capacitive Coupling

- Glitches caused by capacitive coupling between

wires - An aggressor wire switches
- A victim wire is charged or discharged by the

coupling capacitance (cf. charge-sharing

analysis) - An otherwise quiet victim may look like it has

temporarily switched - This is bad if
- The victim is a clock or asynchronous reset
- The victim is a signal whose value is being

latched at that moment - What are some fixes?

- Slide courtesy of Paul Rodman, ReShape

Crosstalk Timing Pull-In

- A switching victim is aided (sped up) by coupled

charge - This is bad if your path now violates hold time
- Fixes include adding delay elements to your path

- Slide courtesy of Paul Rodman, ReShape

Crosstalk Timing Push-Out

- A switching victim is hindered (slowed down) by

coupled charge - This is bad if your path now violates setup time
- Fixes include spacing the wires, using strong

drivers,

- Slide courtesy of Paul Rodman, ReShape

Delay Uncertainty

- Relatively greater coupling noise due to line

dimension scaling - Tighter timing budgets to achieve fast circuit

speed (all paths critical) - ? Train wreck ?
- Timing analysis can be guardbanded by scaling the

coupling capacitance by a Miller Coupling

Factor to account for push-in or push-out.

Homework Q3 (a) explain upper and lower bounds

on the Miller Coupling Factor for a victim wire

that is between two parallel aggressor wires,

assuming step transitions (b) give an estimate

of the ratio (Delay Uncertainty / Nominal Delay)

in the 90nm and 65nm technology nodes.

- Slide courtesy of Kevin Cao, Berkeley

What is Inductance?

- Inductance is the flux induced by current

variation

- Slide courtesy of Massoud/Sylvester/Kawa, Synopsys

Inductance

- When signal is coupled to a ground plane, the

current loop has an inductance. - The inductance is more apparent for upper layer

metals and longer lines - Simple lumped model (more nodes)
- Inductance, makes the interconnect like a

transmission line. - Propagates signal energy, with delay.
- Results in sharper rise times.

VI

VO_RC

VI

VO

VO_ind

T-Line

Slide courtesy of Ken Yang, UCLA

Mutual Inductance

- Magnetic flux couples to many signals
- Not just to immediate adjacent signals (unlike

capacitors.) - Coupling over a larger range.
- Sensitive to geometry and configuration.
- Much bigger lumped model
- Matrix of coupling coefficients not sparse
- Very big problem if we must analyze every signal
- Computationally, we know how, but too complex
- E.g., constrain problem by not building arbitrary

networks

Slide courtesy of Ken Yang, UCLA

Inductance is Important

- If where
- Copper interconnects ? R is reduced
- Faster clock speeds
- Thick, low-resistance (reverse-scaled) global

lines - Chips are getting larger ? long lines ? large

current loops - Frequency of interest is determined by signal

rise time, not clock frequency

Massoud/Sylvester/Kawa, Synopsys

- Slide courtesy of Massoud/Sylvester/Kawa, Synopsys

On-Chip Inductance

- Inductance is a loop quantity
- Knowledge of return path is required, but hard to

determine

Signal Line

Return Path

Massoud/Sylvester/Kawa, Synopsys

- Slide courtesy of Massoud/Sylvester/Kawa, Synopsys

Frequency-Dependent Return Path

- At low frequency, and

current tries to - minimize impedance
- minimize resistance
- use as many returns as possible (parallel

resistances) - At high frequency, and

current tries to - minimize impedance
- minimize inductance
- use smallest possible loop (closest return path)

? L dominates, current returns collapse - Power and ground lines always available as

low-impedance current returns

- Slide courtesy of Massoud/Sylvester/Kawa, Synopsys

Inductance vs. Capacitance

- Capacitance
- Locality problem is easy electric field lines

suck up to nearest neighbor conductors - Local calculation is hard all the effort is in

accuracy - Inductance
- Locality problem is hard magnetic field lines

are not local current returns can be complex - Local calculation is easy no strong geometry

dependence analytic formulae work very well - Intuitions for design
- Seesaw effect between inductance and capacitance
- Minimize variations in L and C rather than

absolutes - E.g., would techniques used to minimize variation

in capacitive coupling also benefit inductive

coupling?

- Slide courtesy of Sylvester/Shepard

Outline

- Introduction
- Motivation/Trends
- Transistors
- Basic logic blocks
- Performance
- Power

Power Dissipation

Lead Microprocessors power continues to increase

100

P6

Pentium proc

10

486

286

8086

Power (Watts)

386

8085

1

8080

8008

4004

0.1

1971

1974

1978

1985

1992

2000

Year

Power delivery and dissipation will be

prohibitive(?)

Courtesy, Intel

Power Density

Power density too high to keep junctions at low

temp(?)

Courtesy, Intel

Power and Energy Figures of Merit

- Power consumption in Watts
- Determines battery life in hours
- Energy density 120W-hrs/kg ?
- Peak power
- Determines power ground wiring designs
- Sets packaging limits (50W / cm2 ? 120W total ?)

(1/Watt ?) - Impacts signal noise margin and reliability

analysis (Why?) - Energy efficiency in Joules
- Rate at which power is consumed over time
- Energy power delay
- Joules Watts seconds
- Lower energy number means less power to perform a

computation at the same frequency

Slide courtesy of Mary Jane Irwin, PSU

Power versus Energy

Watts

Lower power design could simply be slower

time

Watts

Two approaches require the same energy

time

Slide courtesy of Mary Jane Irwin, PSU

Static CMOS Gate Power

- Power dissipation in static CMOS gate 3

components - Dynamic capacitive power
- Still dominant component in current technology
- Charging and discharging the capacitor
- Crowbar current (short-circuit power)
- During a transition, current flows through both P

and N transistors simultaneously for a SHORT

period of time - Slow transitions worsen short-circuit power
- Leakage current
- Even when a device is nominally OFF (VGS0), a

small amount of current is still flowing - With many devices, can add up to hundreds of mW

Slide courtesy of Mary Jane Irwin, PSU

Reducing Dynamic Capacitive Power

- Pdyn CL VDD2 P0?1 f

Slide courtesy of Mary Jane Irwin, PSU

Short-Circuit Power Consumption

Vin

Vout

Isc

CL

Finite slope of the input signal causes a direct

current path between VDD and GND for a short

period of time during switching when both the

NMOS and PMOS transistors are conducting

Slide courtesy of Mary Jane Irwin, PSU

Leakage (Inactive) Power

- Three sources of leakage
- The dominant is the Source-to-Drain leakage

current - Even when VGS 0, a small amount of charge is

still present under the gate - Exponentially related to the gate (and S/D)

voltage - Source/Drain are junctions and some amount of

reverse bias, IS is present - Typically much smaller than S/D leakage
- Gate tunneling leakage
- When tox is only 5-10atoms, easy for tunneling

current to flow - More of an issue sub 0.10-mm technology

Slide courtesy of Ken Yang, UCLA

2001 ITRS Projections of 1/t and Isd,leak for HP,

LP Logic

Projections for Low Power Gate Leakage

- Need for high K driven by Low Power, not High

Performance

Summary Power and Energy Equations

- E CL VDD2 P0?1 tsc VDD Ipeak P0?1 VDD

Ileakage - P CL VDD2 f0?1 tscVDD Ipeak f0?1 VDD

Ileakage

Dynamic power (90 today and decreasing

relatively)

Short-circuit power (8 today and decreasing

absolutely)

Leakage power (2 today and increasing

relatively)

Assignment

- Read Chapters 1, 2 before next time.
- Remember recitation and lab tomorrow

Slide courtesy of Ken Yang, UCLA

EXTRA SLIDES

Typical Mid-Size Chip

- 550k instances (gates placed)