CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC - PowerPoint PPT Presentation

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CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC

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CEG3470 REVISION LECTURE (Some s from Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response) David Harris Harvey Mudd College Spring 2004 – PowerPoint PPT presentation

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Title: CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC


1
CEG3470 REVISION LECTURE(Some slides from
Introduction toCMOS VLSI Design Lecture 4 DC
Transient Response)
  • David Harris
  • Harvey Mudd College
  • Spring 2004

2
Outline
  • Transistor capacitances
  • Transistor properties (current capacitance vs
    size voltage)
  • Inverter transfer function regions of operation

3
The Gate Capacitance
4
Diffusion Capacitance
Channel-stop implant
N
1
A
Side wall
Source
W
N
D
Bottom
x
Side wall
j
Channel
L
Substrate
N
S
A
5
Activity
  • 1)     If the width of a transistor increases,
    the current will 
  • increase decrease not change 
  • 2)     If the length of a transistor increases,
    the current will
  • increase decrease not change
  • 3)     If the supply voltage of a chip increases,
    the maximum transistor current will
  • increase decrease not change
  • 4)     If the width of a transistor increases,
    its gate capacitance will
  • increase decrease not change
  • 5)     If the length of a transistor increases,
    its gate capacitance will
  • increase decrease not change
  • 6)     If the supply voltage of a chip increases,
    the gate capacitance of each transistor will
  • increase decrease not change

6
Transistor Operation
  • Current depends on region of transistor behavior
  • For what Vin and Vout are nMOS and pMOS in
  • Cutoff?
  • Linear?
  • Saturation?

7
nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vgsn gt Vdsn lt Vgsn gt Vdsn gt
8
nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vgsn gt Vtn Vdsn lt Vgsn Vtn Vgsn gt Vtn Vdsn gt Vgsn Vtn
9
nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vgsn gt Vtn Vdsn lt Vgsn Vtn Vgsn gt Vtn Vdsn gt Vgsn Vtn
Vgsn Vin Vdsn Vout
10
nMOS Operation
Cutoff Linear Saturated
Vgsn lt Vtn Vin lt Vtn Vgsn gt Vtn Vin gt Vtn Vdsn lt Vgsn Vtn Vout lt Vin - Vtn Vgsn gt Vtn Vin gt Vtn Vdsn gt Vgsn Vtn Vout gt Vin - Vtn
Vgsn Vin Vdsn Vout
11
pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vgsp lt Vdsp gt Vgsp lt Vdsp lt
12
pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vgsp lt Vtp Vdsp gt Vgsp Vtp Vgsp lt Vtp Vdsp lt Vgsp Vtp
13
pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vgsp lt Vtp Vdsp gt Vgsp Vtp Vgsp lt Vtp Vdsp lt Vgsp Vtp
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
14
pMOS Operation
Cutoff Linear Saturated
Vgsp gt Vtp Vin gt VDD Vtp Vgsp lt Vtp Vin lt VDD Vtp Vdsp gt Vgsp Vtp Vout gt Vin - Vtp Vgsp lt Vtp Vin lt VDD Vtp Vdsp lt Vgsp Vtp Vout lt Vin - Vtp
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
15
Operating Regions
  • Revisit transistor operating regions

Region nMOS pMOS
A
B
C
D
E
16
Operating Regions
  • Revisit transistor operating regions

Region nMOS pMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
17
Noise Margins
  • How much noise can a gate input see before it
    does not recognize the input?

18
Midterm
  • All material in slides on website
  • Test understanding of the material
  • Equation summary (same as for 2007 midterm
    provided)
  • 4 Questions
  • Devices and manufacturing (transistor equations,
    capacitance model, secondary effects, simplified
    process flow, transistor cross section)
  • Wire (RLC, Elmore delay, distributed rc model)
  • Inverter (switching threshold, noise margins,
    delay, power, energy)
  • Buffer sizing (to minimise delay, energy, power)
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