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Designing Sequential Logic Circuits

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Title: Designing Sequential Logic Circuits


1
Chapter 7
Designing SequentialLogic Circuits
Rev 1.0 05/11/03 1.1 5/23/03
2
Sequential Logic
  1. Finite State Machine (FSM)
  2. Pipelined System
  • 2 storage mechanisms
  • Positive feedback (SRAM)
  • Charge-based (DRAM)

3
Naming Conventions
  • In our textbook
  • a latch is Level-sensitive flip-flop
  • a register is Edge-triggered flip-flop
  • There are many different naming conventions
  • For instance, many books call Edge-triggered
    elements flip-flops (asynchronous JK, SR) ? This
    leads to confusion

4
Latch v.s. Register
  • Latch
  • stores data when clock is low (or high)
  • Register
  • stores data when clock rises (on edges)

D
Q
D
Q
Clk
Clk
Clk
Clk
D
D
Q
Q
5
Latches
transparent
hold
hold
hold
6
Latch-Based Design
  • N latch is transparentwhen f 0 hold when f
    1
  • P latch is transparent when f 1 hold when f
    0

f
f
N
P
Logic
Latch
Latch
Logic
7
Timing Definitions
  • (a) Setup time (T_su) the time before the clock
    edge that the D input has to be stable
  • (b) Hold time (T_hold) the time after tue clock
    edge that the D input has to main stable
  • (c) Clock-to-Q delay (Tc-q) the delay from the
    positive clock input to the new value of the Q
    output.

8
Characterizing Timing
t
D
-Q
D
Q
D
Q
Clk
Clk
t
t
C
-Q
C
-Q
Latch
Register
9
Maximum Clock Frequency
T
CLK
tclk-Q tp,comb tsetup
Also tcdreg tcdlogic gt thold tcd
Contamination Delay Minimum delay
tclk-Q tp,comb tsetup lt T
10
Mux-Based Latches
Negative latch (transparent when CLK 0)
Positive latch (transparent when CLK 1)
CLK
11
Mux-Based Latch
12
Mux-Based Latch
CLK
Q
M
CLK
Q
M
CLK
CLK
Non-overlapping clocks
NMOS only
13
Writing into a Static Latch
Use the clock as a decoupling signal, that
distinguishes between the transparent and opaque
states
Forcing the state (can implement as NMOS-only)
Converting into a MUX
14
Master-Slave (Edge-Triggered) Register
Two opposite latches trigger on edge Also called
master-slave latch pair
15
Master-Slave Register
Multiplexer-based latch pair
16
Setup Time
I2-T2 I2 output to T2
17
Clk-Q Delay
2.5
CLK
1.5
D
t
c
- q(lh)
t
c
- q(hl)
Volts
Q
0.5
2
0.5
0.5
1
1.5
2
2.5
0
time, nsec
18
Reduced Clock Load Master-Slave Register
c.f 8 Clock loads in Mater-Slave Register Design
19
Avoiding Clock Overlap
X
CLK
CLK
Q
A
D
B
CLK
CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
20
SR Flip-Flop Cross-Coupled Pairs
NOR-based Set-Reset Flop-Flop
Cross-coupled NORs
21
Cross-Coupled NAND
Cross-coupled NANDs
Added Clock Control
This asynchronous SR FF is not used in datapaths
any more,but is a basic building memory cell
22
Sizing Issues
Output voltage dependence on transistor width
Transient response
23
Storage Mechanisms
Static
Dynamic (charge-based)
24
Clock Overlap
T0-0 T1 and T2 on ? Race Condition
25
Making a Dynamic Latch Pseudo-Static
Adding a weak feedback inverter
26
Clocked CMOS (C2MOS)
Clock 0 1
Master Evaluate Hold
Slave High-impedance Hold Evaluate
Output Previous value stored in CL2 New Value of CL1
Keepers can be added to make circuit
pseudo-static
27
Insensitive to Clock-Overlap
V
V
V
V
DD
DD
DD
DD
M
M
M
M
2
6
2
6
M
0
0
M
4
8
X
X
D
Q
D
Q
M
1
M
1
3
7
M
M
M
M
1
5
1
5
(a) (0-0) overlap
(b) (1-1) overlap
28
True Single-Phase Clocked Register (TSPC)
Negative latch (transparent when CLK 0)
Positive latch (transparent when CLK 1)
A register can be constructed by cascading
Positive and Negative Latches ? 12 transistors
are used!
29
Including Logic in TSPC
Example logic inside the latch
AND latch
30
Positive Edge-triggered Register in TSPC
31
Pipelining
Pipelined
Reference
32
Pipelining
At the expense of Latency (input-to-output
delay) ? Not good for interactive
communicaitons
33
Latch-Based Pipeline
34
7.5.2. NORA CMOS- A logic style for pipelined
structure
(To be added next time)
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