SimpleScalar3.0: Selected Topics aka Hopefully enough to get you started

1
SimpleScalar3.0 Selected Topicsaka Hopefully
enough to get you started

• Michele Co
• September 10, 2001
• Department of Computer Science
• University of Virginia

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Outline

• Overview
• How to register options
• How to register stats
• Gory tour of sim-bpred
• Functional vs. behavioral simulation

3
The Big Picture
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View from a little closer

• main.c main()
• initializes options and stats databases
• register options common to ALL simulators
• sim_reg_options()
• sim_reg_stats()
• sim_check_options()
• sim_init()
• sim_load_prog()
• sim_main()
• exit_now()

• sim-blah.c
• description of how the simulator should behave
• definitions of
• sim_reg_options()
• sim_reg_stats()
• sim_check_options()
• sim_init()
• sim_load_prog()
• sim_main()
• sim_uninit()

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Registering Options

• What is an option?
• Commandline specifiable parameter
• Why register options?
• Interface is provided
• options.c
• opt_reg_int()
• opt_reg_uint()
• opt_reg_flag()
• opt_reg_string()
• and many more ...

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Options Example
in sim-blah.c / maximum number of inst's to
execute / static unsigned int max_insts ... the
n in sim_reg_options() opt_reg_uint(odb, /
name of the opt db / "-maxinst", / option
name / "maximum number of inst's to
execute", / option description
/ max_insts, / address of opt var / 0,
/ default value / TRUE, / print ?
/ NULL / format /)
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Registering Stats

• Whats a stat?
• A statistic you wish to track during the
  simulation
• Why register a stat?
• Interface is provided
• stats.c
• stat_reg_counter()
• stat_reg_formula()
• stat_reg_int()
• stat_reg_uint()
• ... and many more

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Stats Examples
In sim_reg_stats() stat_reg_counter(sdb, /
stats db / "sim_num_insn", / option name
/ "total number of instructions executed",
/ description / sim_num_insn, / addr of
stat var / sim_num_insn, / initial value
/ NULL / format /) (NOTE sim_num_insn
actually declared in main.c)
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Stats Examples (2)
/ declared outside of sim_reg_stats() / static
counter_t sim_num_branches 0 ... stat_reg_coun
ter(sdb, "sim_num_branches", "total number
of branches executed", sim_num_branches,
/ initial value /0, / format /NULL)
stat_reg_formula(sdb, / stats db
/ "sim_IPB", / opt name / "instruction
per branch", / desc / sim_num_insn /
sim_num_branches", / the formula /
NULL / format /)
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sim-bpred - The prelude machine.def
DEFINST(ltenumgt, ltopcodegt,
ltopnamegt, ltoperandsgt, ltfu_reqgt, ltiflagsgt
, ltoutput deps...gt, ltinput deps...gt,
ltexprgt) define ADDU_IMPL \ \
SET_GPR(RD, GPR(RS) GPR(RT)) \
DEFINST(ADDU, 0x42, "addu",
"d,s,t", IntALU, F_ICOMP, DGPR(RD),
DNA, DGPR(RS), DGPR(RT), DNA)
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Branch Definition
define BEQ_IMPL \ \
SET_TPC(CPC 8 (OFS ltlt 2)) \ if
(GPR(RS) GPR(RT)) \ SET_NPC(CPC 8
(OFS ltlt 2)) \ DEFINST(BEQ, 0x05, "beq"
, "s,t,j", IntALU, F_CTRLF_CONDF_DIRJMP, D
NA, DNA, DGPR(RS), DGPR(RT), DNA)
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Memory Definition
define LB_IMPL \ \ sbyte_t
_result \ enum md_fault_type
_fault \ \ _result
READ_BYTE(GPR(BS) OFS, _fault) \ if
(_fault ! md_fault_none) \
DECLARE_FAULT(_fault) \ SET_GPR(RT,
(word_t)(sword_t)_result) \
DEFINST(LB, 0x20, "lb", "t,o(b)", RdPort,
F_MEMF_LOADF_DISP, DGPR(RT), DNA, DNA,
DGPR(BS), DNA)
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sim-bpred macros
/ general purpose registers / define
GPR(N) (regs.regs_RN) define
SET_GPR(N,EXPR) (regs.regs_RN (EXPR)) /
floating point registers, L-gtword,
F-gtsingle-prec, D-gtdouble-prec / define
FPR_L(N) (regs.regs_F.l(N)) define
SET_FPR_L(N,EXPR) (regs.regs_F.l(N)
(EXPR)) define FPR_F(N) (regs.regs_F.f(N))
define SET_FPR_F(N,EXPR) (regs.regs_F.f(N)
(EXPR)) define FPR_D(N) (regs.regs_F.d(N) gtgt
1) define SET_FPR_D(N,EXPR)
(regs.regs_F.d(N) gtgt 1 (EXPR)) / precise
architected memory state help functions
/ define READ_BYTE(SRC, FAULT) \ ((FAULT)
md_fault_none, MEM_READ_BYTE(mem, addr (SRC)))
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sim-bpred main loop
while (TRUE) / maintain r0
semantics / regs.regs_RMD_REG_ZERO
0 / get the next instruction to execute
/ MD_FETCH_INST(inst, mem,
regs.regs_PC) / keep an instruction
count / sim_num_insn / set
default reference address and access mode /
addr 0 is_write FALSE / set
default fault - none / fault
md_fault_none / decode the instruction
/ MD_SET_OPCODE(op, inst)
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Instruction Execution
/ execute the instruction / switch
(op) define DEFINST(OP,MSK,NAME,OPFORM,RES,FLA
GS,O1,O2,I1,I2,I3) \ case OP \
SYMCAT(OP,_IMPL) \ break define
DEFLINK(OP,MSK,NAME,MASK,SHIFT) \ case
OP \ panic("attempted to execute
a linking opcode") define CONNECT(OP) define
DECLARE_FAULT(FAULT) \ fault (FAULT)
break include "machine.def" default
panic("attempted to execute a bogus opcode")

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Sample Expansion of switch()
Based on define BEQ_IMPL \
(0) \ SET_TPC(CPC 8 (OFS ltlt
2)) (1) \ if (GPR(RS)
GPR(RT)) (2) \ SET_NPC(CPC 8 (OFS
ltlt 2)) (3) \ (4) DEFINST(BEQ, 0x05
, "beq", "s,t,j", IntALU, F_CTRLF_CONDF_DI
RJMP, DNA, DNA, DGPR(RS), DGPR(RT), DNA) The
switch expands to case BEQ (generated
by switch) (0) (void)0
(1) if ((regs.regs_R (inst.b gtgt 24) )
(regs.regs_R ((inst.b gtgt 16) 0xff) ) )
(2) (regs.regs_NPC ( (regs.regs_PC) 8
(((int)(( short)(inst.b 0xffff))) ltlt 2) ))
(3) (4) break (from
switch)
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if (fault ! md_fault_none) fatal("fault
(d) detected _at_ 0x08p", fault,
regs.regs_PC) / Memory Instruction /
if (MD_OP_FLAGS(op) F_MEM)
sim_num_refs if (MD_OP_FLAGS(op)
F_STORE) is_write TRUE / Control
Instruction / if (MD_OP_FLAGS(op)
F_CTRL) md_addr_t pred_PC struct
bpred_update_t update_rec sim_num_branches
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if (pred) / get the next
predicted fetch address / pred_PC
bpred_lookup(pred, / branch addr
/regs.regs_PC, / target /target_PC, /
inst opcode /op, / call? /MD_IS_CALL(op),
/ return? /MD_IS_RETURN(op), / stash an
update ptr /update_rec, / stash return
stack ptr /stack_idx) / valid address
returned from branch predictor? / if
(!pred_PC) / no predicted taken target,
attempt not taken target / pred_PC
regs.regs_PC sizeof(md_inst_t)
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bpred_update(pred, / branch addr
/regs.regs_PC, / resolved branch target
/regs.regs_NPC, / taken? /regs.regs_NPC !
(regs.regs_PC sizeof(md_inst_t)), /
pred taken? /pred_PC ! (regs.regs_PC
sizeof(md_inst_t)), / correct pred?
/pred_PC regs.regs_NPC, / opcode
/op, / predictor update pointer
/update_rec) / DLite code
deleted here / / go to the next
instruction / regs.regs_PC
regs.regs_NPC regs.regs_NPC
sizeof(md_inst_t) / finish early? /
if (max_insts sim_num_insn gt
max_insts) return