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A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration

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Title: A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration Author: Jason Last modified by: Administrator Created Date: 2/27/2009 7:25:00 AM – PowerPoint PPT presentation

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Title: A Mixed-Signal/MEMS CMOS Co-Design Flow with MEMS-IP Publishing / Integration


1
A Mixed-Signal/MEMS CMOS Co-Design Flow with
MEMS-IP Publishing / Integration
  • Che-Sheng Chen1 (jason_at_nctutwt.net),
  • Louis Thiam2, Ahmed Hussein Osman2,
  • Kuei-Ann Wen1, Long-Sheng Fan3

1 Inst. Of Electronics, National Chiao Tung
University, Taiwan 2 VCAD, Cadence Design System,
Ltd, USA 3 Inst. Of NanoEngineering and
MicroSystems, National Tsing Hua Unversity,
Taiwan
2
Motivation
FEM Simulation
Design Team Fragmentation
Cross-domain Verification
MEMS Mixed-Signal Digital concurrent design
Integration
Cross-discipline Verification
Methods for efficient use of EDA FEM
3
Outlines
  • MS/MEMS Co-Design Flow Overview
  • MEMS Design Sub-flow
  • MEMS HDL Behavioral Modeling
  • DRC-aware Layout Generation
  • MEMS-IP Publishing/Integration Interface (SIMPLI)
  • Overview
  • Layout Black-boxing
  • HDL Code Encryption
  • Electrical Parasitic Extraction
  • Mixed-Signal Design Sub-flow
  • Correlated Double Sampling Capacitive Readout
  • Summary

4
MS/MEMS Co-design Flow IP Integration Approach
  • MEMS design flow is traditionally top-down
    starting from mechanical characteristics with FEM
    iterations
  • SIPP-SIMPLI interface is providing the bridge
    between MEMS and IC designers
  • IC design flow integrate MEMS components as IP

5
Outlines
  • MS/MEMS Co-Design Flow Overview
  • MEMS Design Sub-flow
  • MEMS HDL Behavioral Modeling
  • Specification-Driven Verification
  • DRC-aware Layout Generation
  • MEMS-IP Publishing/Integration Interface (SIMPLI)
  • Overview
  • Database Structure
  • Code/Layout Encryption
  • Electrical Parasitic Extraction
  • Mixed-Signal Design Sub-flow
  • Correlated Double Sampling Capacitive Readout
  • Summary

6
MEMS Design Sub-flow Top-down approach
7
MEMS Design Sub-flow Details Interleaved
Interaction
8
MEMS HDL Macro-Modeling (1) Interfacing
multi-physics, electrical and MEMS geometries
  • Advantages of HDL behavioral modelling for MEMS
  • Multi-disciplinary language combining physics and
    electrical quantities
  • Open standard to enable re-use and flexible
    mixed-signal simulation environment
  • Ability to create highly parameterizable
    component libraries
  • MEMS geometrical structure description can be
    part of the macro-model
  • Natural convergence toward mixed-signal and
    digital verification

9
MEMS HDL Macro-Modeling (2) Describing
multi-physics equivalence with electrical
  • Each physical equations can be stated
    independently and HDL concurrent process
    statement enables system solution convergence
  • No limit to describe 2nd, 3rd order effects but
    at expense of development time
  • Models can be further enhanced based on results
    extracted from FEM simulation

10
MEMS Functional Verification cockpit Specification
-driven verification
11
MEMS Functional Validation Re-usable and scalable
verification environment
  • Single specification-driven environment for
  • Re-use and automation of verification tasks
  • Synthetic view of design status versus
    specification target
  • Testing environment can be hierarchical
  • Use model similar to digital functional
    verification

12
MEMS Physical Design DRC aware parameterizable
layout generator
Spring Beams Width
Finger Width
Finger Length
Eatch Hole Separation Length
Initial Displacement
Eatch Hole Width Length
Electrode-to-Mass Separation Length
  • SKILL based PCell enables parameterization over
    geometrical parameters with DRC awareness
  • Parameterization linked directly to HDL
    macro-modelling in order to enabled
    schematic-driven layout

13
Outlines
  • MS/MEMS Co-Design Flow Overview
  • MEMS Design Sub-flow
  • MEMS HDL Behavioral Modeling
  • Specification-Driven Verification
  • DRC-aware Layout Generation
  • MEMS-IP Publishing/Integration Interface (SIMPLI)
  • Overview
  • Database Structure
  • Code/Layout Encryption
  • Electrical Parasitic Extraction
  • Mixed-Signal Design Sub-flow
  • Correlated Double Sampling Capacitive Readout
  • Summary

14
SIPP-SIMPLI Subflow concept IP publishing and
integration
15
SIPP-SIMPLI MEMS IP Publishing Subflow Automated
approach
  • SIPP-SIMPLI operated on standard inputs and
    generates views required for Mixed-Signal design
    within Cadence environment
  • SIPP-SIMPLI requires following Cadence tools
  • AMS Incisive for processing HDL models
  • Abstract Generator for black-box layout
    generation
  • Assura for MEMS DRC compliance
  • QRC for MEMS parasitics extraction

16
SIPP-SIMPLI MEMS IP Integration Subflow Automated
approach
  • Only Virtuoso views have to be re-created in
    target PDK which might be packaged differently
    between MEMS IP provider and end-user
  • If PDK package identical between MEMS IP provider
    and IC designer then MEMS IP published by
    SIPP-SIMPLI can be re-used as-is

17
SIPP-SIMPLI Virtuoso Custom Interface Single
interface for publishing and integration
  • Single interface and options for both publishing
    and integration
  • Interface integrated directly with Virtuoso
    platform and compatible with both IC 5.1.41 and
    IC 6.1.3
  • Support batch processing through SKILL APIs for
    entire library management and maintenance

18
SIPP-SIMPLI Layout Processing Layout black-boxing
while enabling accurate integration
19
SIPP-SIMPLI Functional Processing HDL description
encrypted while enabling accurate simulation
20
SIPP-SIMPLI Extraction Processing Layout
extraction while enabling accurate parasitics
21
Outlines
  • MS/MEMS Co-Design Flow Overview
  • MEMS Design Sub-flow
  • Overview
  • MEMS HDL Behavioral Modeling
  • Specification-Driven Verification
  • DRC-aware Layout Generation
  • MEMS-IP Publishing/Integration Interface (SIMPLI)
  • Overview
  • Database Structure
  • Code/Layout Encryption
  • Electrical Parasitic Extraction
  • Mixed-Signal Design Sub-flow
  • Overview
  • Correlated Double Sampling Capacitive Readout
  • Design Summary
  • Conclusion

22
CMOS Mixed-Signal MEMS Subflow concept Meet-in-the
-middle approach
23
CMOS Mixed-Signal MEMS Subflow details Meet-in-the
-middle approach
24
Correlated Double Sampling Readout
  • CDS circuit is suitable for capacitive sensor
    readout
  • Offset cancellation Low frequency noise
    reduction
  • Suitable for following Analog to Digital
    conversion
  • Following another S/H amplifier for proper
    sensitivity
  • Process UMC CMOS-RF 180nm

25
Schematic Capture of Monolithic Integration
26
Schematic-Driven Layout Assembly Hierarchical
layout while reducing LVS errors
  • Schematic-driven layout enables to track
    connectivity between schematic and layout view
  • SIPP-SIMPLI creates a connectivity aware view for
    safe layout integration
  • Custom router could be leveraged since MEMS
    black-box as connectivity and antenna information
  • SIPP-SIMPLI has also LEF file for digital PR
    integration

27
Design Summary
Specifications Conditions Value Unit
Sensor Input Range 2 g
Sampling Freq. lt100 kHz
Sensitivity Vsupply 3.3v 218 mv/g
SFDR Vsupply 3.3v 58.5 dB
Resonate Freq. 6.3 kHz
Output RMS Noise lt 4kHz Vsupply 3.3v 141 uV
Current Consumed Vsupply 3.3v Clock Freq. 100KHz 360 uA
28
The first result of accelerometer (ACC)
fabricated with .18mm 8 CMOS foundry under the
constrain of standard CMOS process.
1 SEM of the ACC
2 Movement of the fingers triggered by external
voltage source
3 Capacitance variation under the excitation of
shaker with 208kHz shaking. ( The green one is
the "PZT reference accelerometer provided as the
reference and the blue one is the performance of
DUT.)
29
Outlines
  • MS/MEMS Co-Design Flow Overview
  • MEMS Design Sub-flow
  • Overview
  • MEMS HDL Behavioral Modeling
  • Specification-Driven Verification
  • DRC-aware Layout Generation
  • MEMS-IP Publishing/Integration Interface (SIMPLI)
  • Overview
  • Data Structure
  • Code/Layout Encryption
  • Electrical Parasitic Extraction
  • Mixed-Signal Design Sub-flow
  • Overview
  • Correlated Double Sampling Capacitive Readout
  • Design Summary
  • Conclusion

30
Conclusion
  • A Mixed Signal-MEMS co-design flow is proposed
    for CMOS/MEMS monolithic integration.
  • A MEMS IP Publishing/Integration interface is
    developed to enable handshaking between MEMS
    Mixed signal circuits.
  • With parametric layout HDL, MEMS/CMOS
    co-optimization can be achieved.
  • A fully integrated CMOS monolithic accelerometer
    has been implemented to demonstrate the proposed
    design flow.

31
Q A
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