Title: Recent Research Progresses in Zhejiang University
1Recent Research Progresses in Zhejiang University
2Outline
- Introduction
- Design For Manufacture
- Formal Verification
- SoC and Platform Design
3Introduction
- Recent RD Activities
- Research in the ICSOC framework
- Research supported by various funding
- RD in joint labs with Samsung and National
Semiconductor - Industrial co-operations
- Recent Educational Activities
- A series of short courses given by 8 professors
from U.S., in IC training center in Hangzhou - Joint master and Ph.D. programs with Royal
Institute of Technology, Sweden (KTH)
4Design For Manufacture
- Lithographic Modeling
- New OPC Methods
- Full-Chip PSM Processing Tool
- Manufacturing Pattern Verification
- DFM of Standard Cells
- New Processes Development
5Lithographic Modeling
- New Test Structure Generation Tool
- Script-driven automatic layout generation
- Testing for various physical settings
- Prepared for fine model characterization
- 130nm, 90nm Lithographic Model Fitting
- Well-matched results with measurements obtained
6Content-Driven OPC Method
- Content-Driven Dissection and Correction
- Processing emphasis is put on functional parts
such as channels - New Dissection Method for Frugal OPC
- Distortion is measured as one criterion for edge
dissection
7Full-chip PSM processing
- Phase Shifter Insertion and Phase Assignment on
Full Chip Level - Red/Blue phase shifter with 0/180 phases
8Sub-100nm Standard Cell Designs
- Sub-100nm Standard Cell DFM Flow and Real Design
Cases - Trial OPC, trial PSM steps are added in the
design flow - Lithographic simulation is performed to analyze
the manufacturability of designed cells in
different environment settings - Cells are being verified in test circuitries on
test chips. -
- A 90nm DFF designed with good
manufacturability
9Test patterns zoomed-in
2D Patterns
1D Patterns
SARFs
10Cells and testing circuitries
8 bit Counter
8 bit Adder
11Tape-out
12Formal Verification
- Verification-Oriented Synthesis
- Combinational Equivalence Checking
- Sequential Equivalence Checking with Retimed
Circuits - Integrated Arithmetic Verification Based on
Abstraction Refinement
13Combinational / Sequential EC
- Using CEC to Verify Sequential Design
- New Algorithms for Retimed Circuit are in
Researching
14Arithmetic Verification
- Arithmetic Verification Based on Abstraction
Refinement - To translate Verilog to abstract-level languages
such as CLU, SVC - Datapath abstraction methods
- Modeling the Datapath Element by,
- ILP constraints
- Presburger arithmetic
- New Hybrid Approaches in CLU Can Be Verified in
UCLID(from CMU)
15SoC and Platform Design
- Embedded CPU Design and Its Development Platform
- CPU core design
- MCU and core-centric applications design
- Co-design platform and full software development
platform - New DSP Core Design
- CPU DSP structure
- Development platformsFPGA
1632-bit embedded CPU
- 7 Pipeline Stages
- High Instruction Density
- Real-Time Response Scheme
- CK520 Enhanced Version
- Hi-speed I-cache/D-cache
- Memory protection
- 64 bit DSP instruction
- Freq. 250MHz
172003????????????41.0??????,??????????
??????????
Growth Rate Y/Y
Revenue100M RMB
99-03 CAGR39.4
SourceCCID Consulting
18?????????????????,????????????????
2003????????? ????
??????????????
????
2074
13.7
???????
27.3
42.7
75.2
1471
35.9
??
75.3
SRAM
FLASH
DRAM
67.7
DSP
??CPU
26.1
???CPU
MCU
27.9
MOS????
26.6
????
??????2074??
CPU?????????????????
19????????????????
??
- 1989??
- ??????????
- ?????????
- IC?????
- 19741984
- ????????????
- ???????
- ??????RC?A?
- 19651973
- IC???????
- ?????????????????
- ????????????????
- 19841988
- UMC??????
- ??IC??????,TSMC???????
- ???????????IC????
????
????
????
????
??
- 19982002
- ??????IC????????
- ????????????????
- ???????????
- 19951998
- ?????????????????
- ???????????
- ST????????????????
- 2003??
- ???????????
- ?????????????????????
????DIR?Digitimes Research, 2004/9
20(No Transcript)
21(No Transcript)
22(No Transcript)
232004?IC?????????
???? ????(??RMB) 2000??????? ???? ?????? ???? 2003????(??RMB) ???????????? ???????????
???? 201 ??111 28.9 171 7387 4962 67.17 21.2 39 5
???? 201 ??64 28.9 171 7387 4962 67.17 21.2 39 5
???? 201 ??26 28.9 171 7387 4962 67.17 21.2 39 5
???? 83 ??68 22.6 73 4876 2297 61.46 18.0 23 4
???? 83 ?? 3 22.6 73 4876 2297 61.46 18.0 23 4
???? 83 ??12 22.6 73 4876 2297 61.46 18.0 23 4
???? 77 ??66 4.7 71 1727 1312 75.97 16.0 (2.9) 6 1
???? 77 ?? 6 4.7 71 1727 1312 75.97 16.0 (2.9) 6 1
???? 77 ?? 5 4.7 71 1727 1312 75.97 16.0 (2.9) 6 1
???? 53 ??36 5.7 49 1863 1566 84.06 2.5 4 0
???? 53 ??12 5.7 49 1863 1566 84.06 2.5 4 0
???? 53 ?? 5 5.7 49 1863 1566 84.06 2.5 4 0
414 414 61.9 364 15853 10837 68.36 57.6 (44.6) 72 10
24???????????????
- ????????????????????????7???????
- ??????????????????,???150??????????
- ?????????????????????,????????IC?????
- ???????????????????,???????????????????
- ??????????,????,????,?????????????
- ????????????(????????)???????????????????
25- ????????????????CPU?????,?????????????
- ???? ??CPU????????????,????????????,?????3C???
- CCore??210?310?510???????,32?RISC?????????,60???
????CCore?? - ??????DSP??????0.18???????16?\24?\
32?DSP??,????????????????? - ???????Co-Star DSP
26??????????
- ????????????????,????????????????????
- ?????
- -????????????????????(SOC)
- -Xwall????????????????????
- -????????????URL??????????????VPN????
27COMIPTM????
- ????????????????????????????????????????,?????
?????????????????????????????????SoC????????????,?
???????????????????????????????????,??????????????
????????????????????
28?????????????????????????????????
- 2003?1?,???????????????????????????????????
- 2003?7?,??????????????????????????????????????????
??????????? - ???????????,?????????,?????????????????,????,????,
?????????? - ???2010?,?????????????4??,????1??????????????????
????????????????
29????????????
30