Low-Power, Low-Phase Noise SiGe HBT Static Frequency Divider Topologies up to 100 GHz

1
Low-Power, Low-Phase Noise SiGe HBT Static
FrequencyDivider Topologies up to 100 GHz

• Ekaterina Laskin, Sean T. Nicolson, Sorin P.
  Voinigescu
• University of Toronto, Canada
• Pascal Chevalier, Alain Chantre, Bernard
  Sautreuil,
• STMicroelectronics, France

2
Outline

• Motivation
• Static divider topology
• Fabrication technologies
• Test setup and results
• Conclusion

3
Motivation

• Applications at 80 GHz
• Phase-locked loop
• Radio circuits
• Comparison of divider topologies
• Technology benchmark

4
Static Divider Topology

• On-chip transformer and matching
• Toggle flip-flop, 50 O output buffer
• 2 different latch designs implemented

5
Integrated Transformer
primary
30µm
secondary

• Stacked design, top 2 metals over substrate
• 30µm square, 1µm spacing, 2µm metal width

6
Transformer Model
primary
k
secondary
substrate model

• Model extracted from geometry using ASITIC
• p - network includes substrate model
• k 0.855 is achieved

7
Input Network Simulation

• Divider input matched 40 100 GHz
• Transformer operational up to 100 GHz

8
Latch Design 1 w/o input EF

• ECL latch
• Inductive peaking
• No split load
• Self-biased
• Resistive input biasing

9
Latch Design 2 with input EF

• Double-EF input buffer

10
Implementation

• Both dividers fabricated in 2 SiGe processes

BiCMOS9
BipX
11
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
12
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
13
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
14
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
15
Fabricated Dividers
with input EF w/out input EF
BiCMOS9
BipX
515µm 473µm 3.3 V 145 mW
502µm 360µm 3.3 V 122 mW
16
Test Setup
0 - 50 GHz
50 - 75 GHz
75 - 100 GHz
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Measurement Results

• Divider self-oscillation frequency

BipX1
BipX2
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Sensitivity Curves
25 C
19
Sensitivity Curves
20
Divider Phase Noise
Input
Output

• 100 GHz
• -90.4 dBc/Hz _at_ 100 kHz offset

• 50 GHz
• -96.4 dBc/Hz _at_ 100 kHz offset

• Phase noise -6 dB with frequency halving

21
Further Improvements
20
MOS-HBT
10
0
-10
Input Power dBm
HBT only
-20
BiCMOS9, HBT only
BiCMOS9, MOS-HBT
BipX, HBT only
10
20
30
40
50
60
70
80
90
100
Input Frequency GHz
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Comparison to Previous Work
23
Conclusion

• 2 SiGe static dividers designed and analyzed in 2
  technologies
• Designed divider operates up to 100 GHz
• Features an integrated transformer operating at
  100 GHz
• Ideal phase noise behaviour
• Low power

24
Thank You
25
Back-up Slides
26
50-O Output Buffer
27
BipX Process Splits
BipX2
BipX1
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Measurement Results

• Divider self-oscillation frequency

BipX1
BipX2
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Measurement Results
with input EF w/out input EF
BiCMOS9 avg 45.9 GHz avg 52.03 GHz s.dev. 1.54 GHz
BipX avg 65.02 GHz avg 72.43 GHz s.dev. 2.06 GHz
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Source Phase Noise _at_ 100GHz
31
BiCMOS Divider