ITRS Roadmap Design System Drivers 2006-7 Worldwide Design TWG

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ITRS Roadmap Design System Drivers2006-7
Worldwide Design TWG
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Whats New in 2005 Design System Drivers

• First worldwide quantitative design technology
  roadmap
• System-level
• Logic/circuit/layout
• Verification
• DFT
• DFM

• First Design For Manufacturability roadmap
• DFM roadmap tool
• Interface with other groups

• New SoC model captures emerging market driver
• Consumer driver
• improves alignment
• with other roadmaps

• Emerging SoC fabric drivers updated
• Analog MIxed-signal
• Embedded memory

In next 10 years, new drivers and technology
limitations will require design technology
overhaul at all abstraction levels
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Design Versus System Drivers
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Design Chapter
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Design Content organization

• Promotion of key design challenges
• Small subset of them as top-level ORTC table

General
Selection
Productivity
Power
DFM
Interference
Reliability
Mapping
System design
Logic/circuit Physical D
Design verification
Design Test
DFM (new)
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New Overall Design Technology Challenges
Near-term (gt 32 nm - 2013) Summary Of Issues
Productivity System level abstraction, functionality spec, platform based design, programmability, integration, AMS Verification executable specification, formal verification, intelligent testbench, coverage-based verification Logic/circuit/layout analog circuit synthesis, multi-objective optimization
Power Dynamic/static, system/circuit, power optimization
Manufacturability Performance/power and device parameter variability, lithography limitations, mask cost, model quality ATE interface test (multi-Gb/s), mixed-signal test, delay BIST, test-volume-reducing DFT
Reliability MTTF-aware design, BISR, soft-error correction
Interference Logic/circuit/layout signal integrity analysis, EMI analysis, thermal analysis
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New Overall Design Technology Challenges
Long term (lt32 nm 2020) Summary Of Issues Summary Of Issues
Productivity Productivity Complete formal verification, complete verification code reuse, complete deployment of functional coverage Tools specific for SOI, non-static-logic, emerging devices Cost-driven design flow Heterogeneous component integration (opt/mech/chem/bio)
Power Power SOI power management
Manufacturability Manufacturability Uncontrollable threshold voltage variability Advanced analog/mixed signal DFT (digital, structural, radio), Statistical and yield-improvement DFT Thermal BIST, system-level BIST
Reliability Reliability Autonomic computing, robust design, SW reliability
Interference Interference Interactions between heterogeneous components (optical, mechanical, chemical, bio, etc.)
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Design Technology Cycle (Pre-Production)

• 10-year cycle

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System-Level Requirements
Source Wolfgang Rosenstiels Team
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Logic/Circuit/Physical Solutions
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DFT Solutions Table
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DFM ? Variability Framework
Actual (bottom-up) / required (top-down)
variability
Performance (delay)
Power (energy)
Gate delay (power)
Wire delay (power)
Intermediate parameters
Intermediate parameters
(Vdd, T)
Rsheet
Vt
NA
Leff
Weff
W
L
t
tOX
tILD
Other TWGs (PIDS, Interconnect, etc.)
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Roadmapping DFM Issues inc. Variability

• Current recommendation
• Not to extend 10 CD control beyond 15
• Below 15 still unclear ? 12 possibly acceptable

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System Drivers Chapter
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ITRS System Drivers Market and Application
Alignment

• ITRS Design Group focuses on roadmapping
• Design Technology challenges and solutions
• Drivers for Silicon Systems design
• ITRS partially aligned by market/application
  driver
• Fabric drivers CPU, DSP/SPU, memory, AMS
• Market drivers consumer mobile, office
• Full alignment will be accomplished in ITRS 2006-7

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ITRS-iNEMI Domain Space
iNEMI (emulators)
Market requirements
ITRS (Drivers)
Tech requirements
Chip level
System level
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Consumer Portable System Driver(Japan Design TWG)
Mobile /Consumer SoC
PE-1
PE-2
PE-n

Main Prc.
Memory
Updated productivity table ? cost
Peripherals
Preserve consistency
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Key Driver Trends

• Power consumption a first-class constraint
• Both for portable and non-portable applications
• Highly parallel architectures
• Increasing number of small processing unit
• System-On-Chip design techniques
• Assemble lots of pre-designed blocks

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--- Overall Requirements (cont.)
SOC Requirements
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Office (MPU) Driver
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Memory Driver
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4. System Drivers Matrix Alignment
Fabrics
HP
CP
MPU
2005
PE(DSP)
Size/weight ratio, battery life
Power, interconnect speed
Memory
AMS
Medical
Network
Portable
Office
Automotive
Defense
Industrial
Markets
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4. System Drivers Matrix Alignment
Fabrics
MPU
2006
PE(DSP)
Memory
AMS
Medical
Network
Portable
Office
Automotive
Defense
Industrial
Markets
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4. System Drivers Matrix Alignment
Fabrics
MPU
2007
PE(DSP)
Memory
AMS
Medical
Network
Portable
Office
Automotive
Defense
Industrial
Markets
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Systems Driver Chapter Future Structure
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Summary ? 2005 Design System Drivers

• First worldwide quantitative design technology
  roadmap
• System-level
• Logic/circuit/layout
• Verification
• DFT
• DFM

• First Design For Manufacturability roadmap
• DFM roadmap tool
• Interface with other groups

• New SoC model captures emerging market driver
• Consumer driver
• improves alignment
• with other roadmaps

• Emerging SoC fabric drivers updated
• Analog MIxed-signal
• Embedded memory

In next 10 years, new drivers and technology
limitations will require design technology
overhaul at all abstraction levels